Rev 1.4, May 28, 2007

Page 2 of 18

SL23EP08

Pin Configuration

16-Pin SOIC/TSSOP

Pin Description

Pin

Number

Pin Name

Pin Type

Pin Description

1

CLKIN

Input

Reference Frequency Clock Input. 5V tolerant input. Weak pull-down

(250k ).

2

CLKA1

Output

Buffered Clock Output, Bank A. Weak pull-down (250k ).

3

CLKA2

Output

Buffered Clock Output, Bank A. Weak pull-down (250k ).

4

VDD

Power

3.3V to 2.5V Power Supply.

5

GND

Power

Power Ground.

6

CLKB1

Output

Buffered Clock Output, Bank B. Weak pull-down (250k ).

7

CLKB2

Output

Buffered Clock Output, Bank B. Weak pull-down (250k ).

8

S2

Input

Select Input, select pin S2. Weak pull-up (250k ).

9

S1

Input

Select Input, select pin S1. Weak pull-up (250k ).

10

CLKB3

Output

Buffered Clock Output, Bank B. Weak pull-down (250k ).

11

CLKB4

Output

Buffered Clock Output, Bank B. Weak pull-down (250k ).

12

GND

Power

Power Ground.

13

VDD

Power

3.3V to 2.5V Power Supply.

14

CLKA3

Output

Buffered Clock Output, Bank A. Weak pull-down (250k ).

15

CLKA4

Output

Buffered Clock Output, Bank A. Weak pull-down (250k ).

16

FBK

Output

PLL Feedback input.