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TUSB212

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SLLSEX5A – AUGUST 2017 – REVISED SEPTEMBER 2017

Product Folder Links: TUSB212

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Copyright © 2017, Texas Instruments Incorporated

Typical Application (continued)

Table 3. Design Parameters (continued)

PARAMETER

VALUE

DC Boost

RDC1

RDC2

Level

Mid DC Level:

RDC1 = DNI

RDC2 = DNI

22 kΩ - 47 kΩ

Do Not Install (DNI)

40 mV Low DC Boost

DNI

DNI

60 mV Mid DC Boost

DNI

22 kΩ - 47 kΩ

80 mV High DC Boost

8.2.2 Detailed Design Procedure

TUSB212 requires a valid reset signal as described in the power supply recommendations section. The capacitor

at RSTN pin is not required if a microcontroller drives the RSTN pin according to recommendations.

VREG pin is the internal LDO output that requires a 0.1-μF external capacitor to GND to stabilize the core.

The ideal AC/DC Boost setting is dependent upon the signal chain loss characteristics of the target platform. The

general recommendation is to start with AC Boost level 0, and then increment to AC Boost level 1, etc. when

needed. Same applies to the DC boost setting where it is recommended to plan for the required pad to change

boost settings.

In order for the TUSB212 to recognize any change to the AC or DC boost settings, the RSTN pin must be

toggled. This is because the EQ and DC_BOOST pins are latched on power up and the pins are ignored

thereafter.

Further D1P has to be shorted to D2P and D1M shorted to D2M on the board for correct functionality of the

device.

Placement of the device is also dependent on the application goal. Table 4 summarizes our recommendations.

Table 4. Platform Placement Guideline

PLATFORM GOAL

SUGGESTED TUSB212 PLACEMENT

Pass USB Near End Mask

Close to measurement point

Pass USB Far End Eye Mask

Close to USB PHY

Cascade multiple TUSB212 to improve device enumeration

Midway between each USB interconnect