TUSB1210 datasheet(16/72 Pages) TI2

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7 Detailed Description

7.1 Overview

The TUSB1210 is a USB2.0 transceiver chip, designed to interface with a USB controller through a ULPI

interface. It supports all USB2.0 data rates High-Speed, Full-Speed, and Low-Speed. Compliant to Host and

Peripheral (OTG) modes. It additionally supports a UART mode and legacy ULPI serial modes. TUSB1210

Integrates a 3.3-V LDO, which makes it flexible to work with either battery operated systems or pure 3.3 V

supplied systems. Also, it has an integrated PLL Supporting 2 Clock Frequencies 19.2 MHz/26 MHz. The ULPI

clock pin (60 MHz) supports input and output clock configurations. TUSB1210 has low power consumption,

optimized for portable devices, and complete USB OTG Physical Front-End that supports Host Negotiation

Protocol (HNP) and Session Request Protocol (SRP).

TUSB1210 is optimized to be interfaced through a 12-pin SDR UTMI Low Pin Interface (ULPI), supporting both

input clock and output clock modes, with 1.8 V interface supply voltage.

TUSB1210 integrates a 3.3 V LDO, which makes it flexible to work with either battery operated systems or pure

3.3 V supplied systems. Both the main supply and the 3.3 V power domain can be supplied through an external

switched-mode converter for optimized power efficiency.

TUSB1210 includes a POR circuit to detect supply presence on VBAT and VDDIO pins. TUSB1210 can be

disabled or configured in low power mode for energy saving.

TUSB1210 is protected against accidental shorts to 5 V or ground on its exposed interface (DP/DM/ID). It is also

protected against up to 20 V surges on VBUS.

TUSB1210 integrates a high-performance low-jitter 480 MHz PLL and supports two clock configurations.

Depending on the required link configuration, TUSB1210 supports both ULPI input and output clock mode:

input clock mode, in which case a square-wave 60 MHz clock is provided to TUSB1210-Q1 at the ULPI interface

CLOCK pin; and output clock mode in which case TUSB1210 can accept a square-wave reference clock at

REFCLK of either 19.2 MHz, 26 MHz. Frequency is indicated to TUSB1210 via the configuration pin CFG. This

can be useful if a reference clock is already available in the system.

7.2 Functional Block Diagram

USB-IP

OTG

1V5

3V3

1V8

POR

VBAT

PLL

PHY

ANA

PHY

DIG

ULPI

REGS

32K

BGAP

& REF

POR

DIG

TEST

OTG

PWR_ FSM

POR

VIO

CTRL

RST_DIG

VDDIO (32)

VBAT (21)

N /C

(24)

VDD15 (12)

VDD18 (28)

VDD33 (20)

DP (18)

DM (19)

ID (23)

(22)

VBUS

( 1) REFCLK

(25) N/C

(17) CPEN

(16) N/C

(15) N/C

VDD18 (30)

PKG Substrate

(Ground )

(14) CFG

(11) CS

( 8) N/C

(27) RESETB

TUSB1210

SLLSE09J – NOVEMBER 2009 – REVISED JULY 2021

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