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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TUSB1064 датащи(PDF) 9 Page - Texas Instruments |
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TUSB1064 датащи(HTML) 9 Page - Texas Instruments |
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9 / 50 page  9 TUSB1064 www.ti.com SLLSF48C – MARCH 2018 – REVISED SEPTEMBER 2019 Product Folder Links: TUSB1064 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated 6.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AUXp/n and SBU1/2 TAUX_PD Switch propagation delay 1400 ps TAUX_SW _OFF Switching time CTL1 to switch OFF. Not including TCTL1_DEBOUNCE. 7500 ns TAUX_SW _ON Switching time CTL1 to switch ON 3000 ns TAUX_INT RA Intra-pair output skew 400 ps USB3.1 and DisplayPort mode transition requirement (GPIO mode) TGP_USB_ 4DP Min overlap of CTL0 and CTL1 when transitioning from USB 3.1 only mode to 4-Lane DisplayPort mode or vice versa 4 µs TCTL1_DE BOUNCE CTL1 and HPDIN debounce time when transitioning from H to L 3 10 ms I2C (SDA and SCL) fSCL I2C clock frequency 1 MHz tBUF Bus free time between START and STOP conditions 0.5 µs tHDSTA Hold time after repeated START condition. After this period, the first clock pulse is generated 0.26 µs tLOW Low period of the I2C clock 0.5 µs tHIGH High period of the I2C clock 0.26 µs tSUSTA Setup time for a repeated START condition 0.26 µs tHDDAT Data hold time 0 µs tSUDAT Data setup time 50 ns tR Rise time of both SDA and SCL signals 120 ns tF Fall time of both SDA and SCL signals 20 × (VI2C/5.5 V) 120 ns tSUSTO Setup time for STOP condition 0.26 µs Cb Capacitive load for each bus line 100 pF |
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