TUSB1064 datasheet(26/50 Pages) TI2

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TUSB1064

SLLSF48C – MARCH 2018 – REVISED SEPTEMBER 2019

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8.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]

Figure 20. DisplayPort Control/Status Registers (0x11)

DP0EQ_SEL

DP2EQ_SEL

R/W/U

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13. DisplayPort Control/Status Registers (0x11)

Bit

Field

Type

Reset

Description

7:4

DP0EQ_SEL

R/W/U

0000

Field selects EQ level for DP lane 0. When EQ_OVERRIDE =

1’b0, this field reflects the sampled state of DPEQ[1:0] pins.

When EQ_OVERRIDE = 1’b1, software can change the EQ

setting for DP lane 0 based on value written to this field.

3:0

DP2EQ_SEL

R/W/U

0000

Field selects EQ level for DP lane 2. When EQ_OVERRIDE =

1’b0, this field reflects the sampled state of DPEQ[1:0] pins.

When EQ_OVERRIDE = 1’b1, software can change the EQ

setting for DP lane 2 based on value written to this field.

8.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]

Figure 21. DisplayPort Control/Status Registers (0x12)

Reserved

SET_POWER_STATE

LANE_COUNT_SET

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. DisplayPort Control/Status Registers (0x12)

Bit

Field

Type

Reset

Description

Reserved

6:5

SET_POWER_STATE

R/U

This field represents the snooped value of the AUX write to

DPCD address 0x00600. When AUX_SNOOP_DISABLE = 1’b0,

the TUSB1064 will enable/disable DP lanes based on the

snooped value. When AUX_SNOOP_DISABLE = 1’b1, then DP

lane enable/disable are determined by state of DPx_DISABLE

registers, where x = 0, 1, 2, or 3. This field is reset to 2’b00 by

hardware when CTLSEL1 changes from a 1’b1 to a 1’b0.

4:0

LANE_COUNT_SET

R/U

00000

This field represents the snooped value of AUX write to DPCD

address 0x00101 register. When AUX_SNOOP_DISABLE =

1’b0, TUSB1064 will enable DP lanes specified by the snoop

value. Unused DP lanes will be disabled to save power. When

AUX_SNOOP_DISABLE = 1’b1, then DP lanes enable/disable

are determined by DPx_DISABLE registers, where x = 0, 1, 2, or

3. This field is reset to 0x0 by hardware when CTLSEL1

changes from a 1’b1 to a 1’b0.

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