TAS5713 datasheet(43/72 Pages) TI2

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TAS5713

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SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010

Table 4. Serial Control Interface Register Summary (continued)

NO. OF

INITIALIZATION

SUBADDRESS

CONTENTS

BYTES

VALUE

0x73

ch1 left_channel_mixer

u[31:26], left_mix_1[25:0]

0x0080 0000

0x74

ch2 inline mixer

u[31:26], in_mix2[25:0]

0x0080 0000

0x75

inline_DRC_en_mixer_ch2

u[31:26], in_mixdrc_2[25:0]

0x0000 0000

0x76

ch2 left_chanel mixer

u[31:26], left_mix1[25:0]

0x0000 0000

0x77

ch2 right_channel_mixer

u[31:26], right_mix_1[25:0]

0x0080 0000

0x78–0xF7

Reserved(3)

0xF8

Update dev address key

Dev Id Update Key[31:0] (Key = 0xF9A5A5A5)

0x0000 0000

0xF9

Update dev address reg

u[31:8],New Dev Id[7:0] (New Dev Id = 0x38 for

0x0000 0036

TAS5713)

0xFA–0xFF

Reserved(3)

0x0000 0000

All DAP coefficients are 3.23 format unless specified otherwise.

Registers 0x3B through 0x46 should be altered only during the initialization phase.

CLOCK CONTROL REGISTER (0x00)

The clocks and data rates are automatically determined by the TAS5713. The clock control register contains the

autodetected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency.

Table 5. Clock Control Register (0x00)

FUNCTION

–

fS = 32-kHz sample rate

–

Reserved(1)

–

Reserved(1)

–

fS = 44.1/48-kHz sample rate

(2)

–

fS = 16-kHz sample rate

–

fS = 22.05/24-kHz sample rate

–

fS = 8-kHz sample rate

–

fS = 11.025/12-kHz sample rate

–

MCLK frequency = 64 × fS

(3)

–

MCLK frequency = 128 × fS

(3)

–

MCLK frequency = 192 × fS

(4)

–

MCLK frequency = 256 × fS

(2) (5)

–

MCLK frequency = 384 × fS

–

MCLK frequency = 512 × fS

–

Reserved(1)

–

Reserved(1)

–

Reserved(1)

–

Reserved(1)

(1)

Reserved registers should not be accessed.

(2)

Default values are in bold.

(3)

Only available for 44.1-kHz and 48-kHz rates

(4)

Rate only available for 32/44.1/48-KHz sample rates

(5)

Not available at 8 kHz

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