PM8805 datasheet(23/45 Pages) STMICROELECTRONICS

23 / 45 page

DS12813 Rev 1

23/45

PM8805

PM8805 overview

the Rdson. The second circuit is a fast ZCD comparator, with a typical response time of 10

us (Td_ZCD), which is in charge of determining the polarity of the current.

Four ZCD comparators are also present across the low-side MOSFETs of the bridges.

The control logic checks the output of the ZCD comparators to determine which bridge to

turn on/off. Starting from a default all-off condition, each bridge leg is turned on only if both

the ZCD advertises a positive current flowing from PoE to the load, and at the same time the

complementary ZCD comparators report a zero current condition (reverse biased diodes).

Only valid input combinations are considered valid for the bridge activation, i.e the IEEE

standard ModeA (IN12 - IN36) and ModeB (IN45 - IN78) configurations.

For example, if both IN12=48 V and IN45=48 V while IN36=0 V and IN78=hi-Z, only the

high-side MOSFET on IN12 and the low-side MOSFET on IN36 are turned on, while all the

other MOSFETs, including the one connected to the high side of IN45, are kept off. This is

the typical case when a PSE is turning on only one of the two pair-sets, while both share the

same common rail on the high side. This prevents the current flowing on a pair which is not

supposed to supply current.

In case any ZCD comparator reports a zero or reverse current condition, both the high-side

and the low-side MOSFETs of that bridge are instantaneously turned off.

The active bridge ensures a very low unbalance between pairs, since the contribution on the

unbalance is only due to the Rdson mismatch of different bridges. This is generally much

lower than the unbalance due to diode bridges, where the difference in the forward voltage

may cause big differences in the current flowing in the 2-pair sets. Moreover, the MOSFET

channel resistance has an intrinsic ballasting effect on the current, further improving the

overall balancing.

In order to comply with the IEEE802.3bt pair-to-pair current unbalance requirements, the PD

must not exceed Icon_2P_unb for more than 50 ms. A design guideline is provided by the

standard in order to facilitate the compliance at the maximum power levels for each PD

class. It is recommended that the pair with maximum resistance (Rpair_max) does not

exceed the values reported in Table 8.

The contribution to the pair-to-pair unbalance of the PM8805 is Unbal (30% max.) with no

offset voltage contribution, typical of diode bridges. So, it should be straightforward to

achieve the most stringent requirements (75% for class 8), just taking care not to introduce a

large resistance difference between pairs on the application board. Consider that the only

components which may introduce unbalance are the data transformer and the PCB traces,

whose contribution to the unbalance just needs to be lower than 45% (worst case for class

8).

In general, depending on the PD Type and class, the relevant PD electrical parameters are

summarized in Table 9.

Table 8. PD unbalance specification

PD class

Icon_2P_unb (mA)

Rpair_max. (

Ω)

Class 5

550

2.20*Rpair_min+0.125

Class 6

682

2.01*Rpair_min+0.105

Class 7

777

1.80*Rpair_min+0.080

Class 8

925

1.75*Rpair_min+0.080

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