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L99LD01 датащи(PDF) 55 Page - STMicroelectronics |
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L99LD01 датащи(HTML) 55 Page - STMicroelectronics |
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55 / 69 page ![]() DocID025319 Rev 3 55/69 L99LD01 SPI electrical characteristics 68 6.3 Dynamic characteristics The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V S ≤ 24 V; all outputs open; Tj = -40 °C to 150 °C, unless otherwise specified. For definition of the parameters please see Figure 29 and Figure 30. Table 34. SPI dynamic characteristics Symbol Parameter Test condition Min Typ Max Unit tCSNQVL DO enable from tristate to low level CDO = 100 pF; IDO =1 mA; pull-up load to VCC; VCC1 =5.0 V 100 250 ns tCSNQVH DO enable from tristate to high level CDO = 100 pF; IDO =- 1 mA; pull-down load to GND; VCC1 =5.0 V 100 250 ns tCSNQTL DO disable from low level to tristate CDO = 100 pF; IDO =4 mA; pull-up load to VCC; VCC1 =5.0 V 380 450 ns tCSNQTH DO disable from high level to tristate CDO = 100 pF, IDO = -4 mA; pull-down load to GND; VCC1 =5.0 V 380 450 ns tCLKQV CLK falling until DO valid VDO <0.3 VCC or VDO >0.7 VCC; CDO =5 pF; VCC1 =5.0 V ns VDO <0.3 VCC or VDO >0.7 VCC; CDO = 100 pF; VCC1 =5.0 V ns tSCSN CSN setup time, CSN low before rising edge of CLK VCC1 = 5.0 V 400 ns tSDI DI setup time, DI stable before rising edge of CLK VCC1 = 5.0 V 200 ns tHCLK minimum CLK high time VCC1 = 5.0 V 115 ns tLCLK minimum CLK low time VCC1 = 5.0 V 115 ns tHCSN minimum CSN high time VCC1 =5.0 V 4 µs tSCLK CLK setup time before CSN rising VCC1 = 5.0 V 400 ns tr DO DO rise time CDO = 100 pF; VCC1 = 5.0 V 80 140 ns tf DO DO fall time CDO = 100 pF; VCC1 = 5.0 V 50 100 ns tr in rise time of input signal DI, CLK, CSN VCC1 = 5.0 V 100 ns tf in fall time of input signal DI, CLK, CSN VCC1 = 5.0 V 100 ns |
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