L99PM62XP datasheet(33/98 Pages) STMICROELECTRONICS

33 / 98 page

L99PM62XP

Description

Doc ID 16363 Rev 4

33/98

2.9.4

CAN receive only mode

With the CAN_rec_only bit in control register 4 it is possible to disable the CAN transmitter

in active mode. In this mode it is possible to listen to the bus but not sending to it. The

receiver termination network is still activated in this mode.

2.9.5

CAN looping mode

If the CAN_Loop_en bit in control register 4 is set the TXDC input is mapped directly to the

RXDC pin. This mode can be used in combination with the CAN receive only mode, to run

diagnosis for the CAN protocol handler of the micro controller.

2.10

Serial peripheral interface (ST SPI standard)

A 24 bit SPI is used for bi-directional communication with the micro controller.

During active mode, the SPI

●

Triggers the watchdog

●

Controls the modes and status of all L99PM62XP modules (incl. input and output

drivers)

●

Provides driver output diagnostic

●

Provide L99PM62XP diagnostic (incl. over temperature warning, L99PM62XP

operation status)

The SPI can be driven by a micro controller with its SPI peripheral running in following

mode:

CPOL = 0 and CPHA = 0.

For this mode input data is sampled by the low to high transition of the clock CLK, and

output data is changed from the high to low transition of CLK.

This device is not limited to micro controller with a built-in SPI. Only three CMOS-compatible

output pins and one input pin is needed to communicate with the device. A fault condition

can be detected by setting CSN to low. If CSN = 0, the DO-pin reflects the global error flag

(fault condition) of the device.

Chip select not (CSN)

The input pin is used to select the serial interface of this device. When CSN is high, the

output pin (DO) is in high impedance state. A low signal activates the output driver and a

serial communication can be started. The state during CSN = 0 is called a communication

frame.

If CSN = low for t > tCSNfail the DO output is switched to high impedance in order to not block

the signal line for other SPI nodes.

Serial data in (DI)

The input pin is used to transfer data serial into the device. The data applied to the DI is

sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register.

At the rising edge of the CSN signal the contents of the shift register is transferred to Data

Input Register. The writing to the selected data input register is only enabled if exactly 24

bits are transmitted within one communication frame (i.e. CSN low). If more or less clock

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