L99PM62XP datasheet(17/98 Pages) STMICROELECTRONICS

17 / 98 page

L99PM62XP

Description

Doc ID 16363 Rev 4

17/98

Except for the disabled watchdog, the Flash mode is identical to active mode and all device

features are available.

The mode can be entered if one of the following conditions is applied:

●

VTxDL > VFlash

●

VTxDC > VFlash

At exit from Flash mode (VTxD < VFlash) no NReset pulse is generated and the watchdog

starts with a long open window.

Note:

Setting both TxDL and TxDC to high voltage levels (> VFlash) is not allowed

2.2.3

V1 standby mode

The transition from active mode to V1 standby mode is controlled by SPI.

To supply the micro controller in a low power mode, the voltage regulator 1 (V1) remains

active. In order to reduce the current consumption, the regulator goes in low current mode

as soon as the supply current of the microcontroller goes below the Icmp current threshold.

At this transition, the L99PM62 also deactivates the internal watchdog.

Relay outputs, LIN and CAN transmitters is switched off in V1 standby mode. High-side

outputs and the V2 regulator remain in the configuration programmed prior to the standby

command.

A cyclic supply of external contacts and a synchronized monitoring of the contact state can

be activated and configured by SPI.

In V1 standby mode various wake up sources can be individually programmed. Each wake

up event puts the device into active mode and forces the RxDL/NINT pin to a low level

indicating the wake-up condition to the microcontroller.

After power ON reset (POR) all wake up sources are activated by default except the

periodic interrupt/wake timer.

With the interrupt timer the micro controller can be forced from ‘stop’ to ‘run’ after a

programmable period. The RxDL/NINT pin is forced low after the timer is elapsed. The

L99PM62XP enters active mode and is awaiting a valid watchdog trigger.

Both internal timers can be used for this feature.

The interrupt timer (TINT) at pin RxDL/NINT is only available in V1 standby mode.

Note:

Inputs TxDL, TxDC and CSN must be at high level or at high impedance in order to achieve

minimum standby current in V1 standby mode.

Inputs DI and CLK must be at GND or at high impedance to achieve minimum standby

current in V1 standby mode.

Interrupt

The interrupt signal (linked to RxDL/NINT internally) indicates a wake-up event from V1

standby mode. In case of a wake-up by Wake-up Inputs, activity on LIN or CAN, SPI access

or timer-interrupt the NINT pin is pulled low for 56 µs.

In case of V1 standby mode and (IV1 > Icmp), the device remains in standby mode, the V1

regulator switches to high current mode and the watchdog starts. No Interrupt signal is

generated.

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