L99LDLH32 datasheet(19/142 Pages) STMICROELECTRONICS

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DS12879 Rev 6

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L99LDLH32

Linear current sources

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The L99LDLH32 features one analog pin (VREF_PRE_REG) providing a voltage proportional

to the maximum output voltage of active channels plus the required drop voltage across the

current regulator required for proper regulation (~1.4 V). This signal can be used in

combination with an analogue discrete circuit to close directly the feedback loop with an

external DC/DC converter.

For applications with a common DC/DC converter for several L99LDLH32 devices, the

VREF_PRE_REG output signal is buffered, therefore, it can be combined in wired-OR with

VREF_PREG_REG output signals from other devices to make sure only the highest reference

voltage is fed back to the external DC/DC converter.

A dedicated Application Note is available for more information on this feature and how to

use in application.

4.4

Channel output gradual delay

The L99LDLH32 features the output gradual delay, which consists in gradual turning on of

the current generators. In case of driving several outputs simultaneously, the output gradual

delay is applied in order to lower the current transients and improve device emissions. This

feature can be activated – for all the channels - through one dedicated bit (OUT_DELAY,

see FTP/RAM memory map, Chapter 7).

In case one or more channels are not enabled, gradual delay is increased according to the

number of channels turned OFF.

The Gradual Delay concept is valid in PWM mode as well: in this case, the PWM waveform

is shifted and the gradual delay is applied also when channel is turned OFF.

The output gradual delay feature is valid both for Normal / Bus mode and Fail Safe / Stand

Alone Mode. In this latter case, Direct Input (DIN) controls output channels as per FTP

setting (DIN_MAP_CHx, 1bit - see FTP/RAM memory map, Chapter 7): it is suggested to

apply the output gradual feature if minimum PWM on time is ≥ 20 µs. Otherwise, it is

suggested to disable the feature by the dedicated bit.

The delay between each output is showed in Figure 5.

Table 2. Minimum channel drop-out voltage at max current vs TJ

TJ [°C]

VOUTx_DROP [V]

125

1.05

-40

0.95

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