PCM5121 datasheet(11/121 Pages) TI2

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XSMT

0.9 * DV

<20ns

0.1 * DV

tSCKH

System Clock

(SCK)

tSCKL

"L"

"H"

0.3*DVDD

0.7*DVDD

tSCY

PCM5121, PCM5122

www.ti.com

SLAS763C – AUGUST 2012 – REVISED OCTOBER 2018

Product Folder Links: PCM5121 PCM5122

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7.6 Timing Requirements: SCK Input

Figure 1 shows the timing requirements for the system clock input. For optimal performance, use a clock source with low

phase jitter and noise.

MIN

NOM

MAX

UNIT

tSCY

System clock pulse cycle time

1000

tSCKH

System clock pulse width, high

DVDD = 1.8 V

DVDD = 3.3 V

tSCKL

System clock pulse width, low

DVDD = 1.8 V

DVDD = 3.3 V

7.7 Timing Requirements: XSMT

MIN

NOM

MAX

UNIT

Rise time

Fall time

(1)

One sample time is defined as the reciprocal of the sampling frequency. 1 × tS = 1 / fS

(2)

With the appropriate P coefficient setting, the PLL accepts up to 50 MHz. This clock is then divided to meet the

≤ 20-MHz requirement.

See PLL Calculation.

7.8 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DATA FORMAT (PCM MODE)

Audio data interface format

I2S, left-justified, right-justified, and

TDM

Audio data bit length

16, 20, 24, 32-bit acceptable

Audio data format

MSB first, twos-complement

Sampling frequency(1)

384

kHz

CLOCKS

System clock frequency

64, 128, 192, 256, 384, 512, 768,

1024, 1152, 1536, 2048, or 3072

fSCK, up to 50 Mhz

PLL input frequency (2)

Clock divider uses fractional divide

D > 0, P=1

6.7

MHz

Clock divider uses integer divide

D = 0, P=1

MHz

Figure 1. Timing Requirements for SCK Input

Figure 2. XSMT Timing for Soft Mute and Soft Un-Mute

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