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PCM5121 датащи(PDF) 80 Page - Texas Instruments

номер детали PCM5121
подробное описание детали  PCM512x 2-VRMS DirectPath™, 112-dB and 106-dB Audio Stereo DACs With 32-Bit, 384-kHz PCM Interface
PDF  121 Pages
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производитель  TI2 [Texas Instruments]
домашняя страница  https://www.ti.com
Logo TI2 - Texas Instruments

PCM5121 датащи(HTML) 80 Page - Texas Instruments

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PCM5121, PCM5122
SLAS763C – AUGUST 2012 – REVISED OCTOBER 2018
www.ti.com
Product Folder Links: PCM5121 PCM5122
Submit Documentation Feedback
Copyright © 2012–2018, Texas Instruments Incorporated
RSV
Reserved
Reserved. Do not access.
DOSR[6:0]
OSR Clock Divider
These bits set the source clock divider value for the OSR clock. These bits are ignored in clock auto set mode.
Default value: 0000000
0000000: Divide by 1
0000001: Divide by 2
...
1111111: Divide by 128
Table 77. Page 0 / Register 32
Dec
Hex
b7
b6
b5
b4
b3
b2
b1
b0
32
20
RSV
DBCK6
DBCK5
DBCK4
DBCK3
DBCK2
DBCK1
DBCK0
Reset Value
0
0
0
0
0
0
0
RSV
Reserved
Reserved. Do not access.
DBCK[6:0]
Master Mode BCK Divider
These bits set the SCK divider value to generate I2S master BCK clock.
Default value: 0000000
0000000: Divide by 1
0000001: Divide by 2
...
1111111: Divide by 128
Table 78. Page 0 / Register 33
Dec
Hex
b7
b6
b5
b4
b3
b2
b1
b0
33
21
DLRK7
DLRK6
DLRK5
DLRK4
DLRK3
DLRK2
DLRK1
DLRK0
Reset Value
0
0
0
0
0
0
0
0
DLRK[7:0]
Master Mode LRCK Divider
These bits set the I2S master BCK clock divider value to generate I2S master LRCK clock.
Default value: 00000000
00000000: Divide by 1
00000001: Divide by 2
...
11111111: Divide by 256
Table 79. Page 0 / Register 34
Dec
Hex
b7
b6
b5
b4
b3
b2
b1
b0
34
22
RSV
RSV
RSV
I16E
RSV
RSV
FSSP1
FSSP0
Reset Value
0
0
0
RSV
Reserved
Reserved. Do not access.
I16E
16x Interpolation
This bit enables or disables the 16x interpolation mode
Default value: 0
0: 8x interpolation



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