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LP2992IM5-5.0/NOPB датащи(PDF) 28 Page - Texas Instruments |
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LP2992IM5-5.0/NOPB датащи(HTML) 28 Page - Texas Instruments |
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28 / 43 page ![]() 7.4 Layout 7.4.1 Layout Guidelines • Bypass the input pin to ground with a bypass capacitor. • The optimum placement of the bypass capacitor is closest to the VIN of the device and GND of the system. Care must be taken to minimize the loop area formed by the bypass capacitor connection, the VIN pin, and the GND pin of the system. • For operation at full-rated load, use wide trace lengths to eliminate IR drop and heat dissipation. 7.4.2 Layout Examples V IN GND PLANE C IN C BYPASS BYPASS ON/OFF V OUT C OUT Figure 7-15. Layout Diagram LP2992 SNVS171L – NOVEMBER 2001 – REVISED FEBRUARY 2025 www.ti.com 28 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: LP2992 |
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