STA1080 datasheet(11/127 Pages) STMICROELECTRONICS

11 / 127 page

DS13319 Rev 2

11/127

STA108x, STA109x

System description

126

System description

2.1

Processor MCU

Accordo2 processing capability relies on an ARM Cortex-R4 running up to 600 MHz,

delivering up to 1000 MIPS with very low heat dissipation requirements. The MCU has 32

KB of instruction cache and 32 KB of data cache, as well as 32 KB + 32 KB of TCM Memory

dedicated respectively to instructions and data for high throughput and low latency tasks.

2.2

Memory controller

2.2.1

Embedded memory

Accordo2 embeds 1.25 MB of 64-bits SRAM memory clocked at 200 MHz, which can be

used for data or code storage delivering 1.6 GB/s throughput.

Embedded memory can be used in conjunction with execution In Place (XIP) NOR devices

to implement cost effective solutions. The whole embedded memory is also cacheable and

can be accessed by DMA.

2.2.2

SDRAM controller

SDRAM controller supports SDRAM JEDEC interface 16-bit (STA108x) or 32-bit (STA109x)

wide, clocked at up to 166 MHz, which allows to interface automotive SDRAM memory

devices to handle high footprint applications.

Such memory is cacheable, and can be accessed by DMA.

2.2.3

SQI executable in place

The SQIO controller allows interfacing Serial Quad I/O flash memories up to 133MHz (SDR)

The main features are:



Direct flash memory access



Fast memory access through page buffer (256 bytes)



Programmable single or quad I/O flash interface

SQI memory space can be partitioned to reserve a portion of the NOR device to the Secure

CAN Subsystem.

2.2.4

Parallel memory interface

FSMC static memory controller, provides a generic 16-bit parallel interface suitable to

connect to NOR devices as well as SRAM and NAND devices. This peripheral allows

execution in-place from NOR/SRAMs, as well as DMA accesses.

NOR memory space can be partitioned so to reserve a portion of the parallel NOR device to

the Embedded Vehicle Interface subsystem.

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