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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STA1080 датащи(PDF) 90 Page - STMicroelectronics |
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STA1080 датащи(HTML) 90 Page - STMicroelectronics |
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90 / 127 page  Electrical Characteristics STA108x, STA109x 90/127 DS13319 Rev 2 4.19.1 SQI Bit Clock Generation The SQI serial bitclock (SQI_SCK) is generated dividing the peripheral input master clock SQI_CLK. The division factor is controlled by the bits [7:0] of the SQI_CONF_REG1 of the SQI controller: Bit 7:0 SPI_CLK_DIV (SQI master clock divider) 0x00, 0x01 = divide by 2 0x02, 0x03 = divide by 4 0x04, 0x05 = divide by 6 … 0xFE, 0xFF = divide by 256 The SQI peripheral is accessed by the system bus masters through the bus matrix. The clock of the bus matrix is HCLK. A frequency clock relationship must be respected in the configuration of the SQI clock between SQI_CLK and HCLK, as reported in the Chapter 4.19.2: Clock Constraint. This condition must be respected to ensure that the system works correctly in all voltage, temperature and process conditions. SQI_CLK Clock Generation The SQI master clock SQI_CLK is generated dividing the PLL2 output clock, according to the following picture: Figure 29. PLL2 Clock Diagram ÷3 ÷6 ÷12 ÷5 ÷7 ÷26 ÷25 ÷4 PLL2 FVCOBY2 PHI Enable Enable Enable Enable Enable 2 3 4 3 4 1 6 6 5 5 RING OSC MXTAL RING OSC MXTAL Enable 52M_CLK (UART, MSP, I2C) SSP_CLK Enable CANSS_CLK SRCR3_CR[2:0] = MODECR SRCR3_CR[2:0] = MODECR GAPGPS02601 RING OSC MXTAL SRCR3_CR[2:0] = MODECR 1 M3_CLK CLCD_CLK SQI_CLK SDMMC_CLK AudioSS_512Fs_CLK ÷2 DSP_CLK AudioSS_MCLK AudioSS_256Fs_CLK |
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