L9924L datasheet(68/84 Pages) STMICROELECTRONICS

68 / 84 page

SPI interface

L9924L

68/84

DocID028840 Rev 3

12.4.9

DEVICE ID register [0x1F]

This register contains chip and communication protocol configuration:

12.4.10

SYSTEM / UNLOCK register [0x01]

This register contains some unlock bits to allow a write access to the relevant bits of register

0x02 or register 0x06.

Table 50. DEVICE ID register [0x1F]

Bit

Reset value

Description

Reserved

LIN_PROT_DENIED_OTP

0: LIN available

1: LIN not available

APPL_24V_DENIED_OTP

0: 24V supported

1: 24V not supported

ProtSel

PROT_SEL pin image

8RC

RC pin image: if the pin is used for a

communication protocol its value follows

the status of the line

7-0

Sil_Revision

Silicon revision

Table 51. SYSTEM / UNLOCK register [0x01]

Bit

Reset value

Description

Reserved

UNLOCK_SEL24V_EN

0 (WO

Write 1 to enable the write access to

SEL24V_EN bit of register 2

Reserved

UNLOCK WDG Config REG_06

0 (WO)

Write 1 to enable the write access to the

WDG Config register (0x06)

UNLOCK WDG: Init Time-Out

Disable

0 (WO)

Writing '1' to this bit enables a write

access to the WDG INIT ENABLE bit of

System Operation register (0x02)

UNLOCK_WDG_FAIL_REST_µC

0 (WO)

Writing '1' to this bit enables a write

access to the WDG_FAIL_REST-uC bit of

System Operation register (0x02)

7-5

Reserved

UNLOCK EPONA Cfg-REGs SW

Reset Capability

0 (WO)

Writing '1' to this bit enables a write

access to the SW_RESET bit of System

Operation register (0x02)

3-1

Reserved

UNLOCK_SYST_POWER_OFF

0 (WO)

Writing '1' to this bit enables a write

access to the POWER_OFF bit of

System Operation register (0x02)

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