8.2.1.2 Input Considerations

Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do

not exceed the maximum input voltage range found in the Absolute Maximum Ratings.

Unused inputs must be terminated to either VCC or ground. The unused inputs can be directly terminated if the

input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used

sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is

used for a default state of LOW. The drive current of the controller, leakage current into the CD74ACT157 (as

specified in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10kΩ

resistor value is often used due to these factors.

The CD74ACT157 has CMOS inputs and thus requires fast input transitions to operate correctly, as defined in

the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power

consumption, and reduction in device reliability.

Refer to the Feature Description section for additional information regarding the inputs for this device.

8.2.1.3 Output Considerations

The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will

decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground

voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output

voltage as specified by the VOL specification in the Electrical Characteristics.

Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected

directly together. This can cause excessive current and damage to the device.

Two channels within the same device with the same input signals can be connected in parallel for additional

output drive strength.

Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.

Refer to the Feature Description section for additional information regarding the outputs for this device.

8.2.2 Detailed Design Procedure

1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the

device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout

section.

2. Verify that the capacitive load at the output is ≤ 50pF. This is not a hard limit; by design, however, it will

optimize performance. This can be accomplished by providing short, appropriately sized traces from the

CD74ACT157 to one or more of the receiving devices.

3. Verify that the resistive load at the output is larger than (VCC / IO(max))Ω. Doing this prevents the maximum

output current from the Absolute Maximum Ratings from being violated. Most CMOS inputs have a resistive

load measured in MΩ; much larger than the minimum calculated previously.

4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,

can be calculated using the steps provided in the CMOS Power Consumption and Cpd Calculation

application note.

8.2.3 Application Curve

A/B

G

xY

xA

xB

Figure 8-2. Application Timing Diagram

www.ti.com

CD74ACT157

SCHS340D – MARCH 2003 – REVISED JULY 2025

Copyright © 2025 Texas Instruments Incorporated

Submit Document Feedback

13

Product Folder Links: CD74ACT157