7.3 Feature Description

7.3.1 Balanced CMOS Push-Pull Outputs

This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink

and source similar currents. The drive capability of this device may create fast edges into light loads, so routing

and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable

of driving larger currents than the device can sustain without being damaged. It is important to limit the output

power of the device to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute

Maximum Ratings must be followed at all times.

Unused push-pull CMOS outputs must be left disconnected.

7.3.2 TTL-Compatible CMOS Inputs

This device includes TTL-compatible CMOS inputs. These inputs are specifically designed to interface with TTL

logic devices by having a reduced input voltage threshold.

TTL-compatible CMOS inputs are high impedance and are typically modeled as a resistor in parallel with

the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the

maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given

in the Electrical Characteristics, using Ohm's law (R = V ÷ I).

TTL-compatible CMOS inputs require that input signals transition between valid logic states quickly, as defined

by the input transition time or rate in the Recommended Operating Conditions table. Failing to meet this

specification will result in excessive power consumption and could cause oscillations. More details can be found

in the Implications of Slow or Floating CMOS Inputs application report.

Do not leave TTL-compatible CMOS inputs floating at any time during operation. Unused inputs must be

terminated at VCC or GND. If a system will not be actively driving an input at all times, a pull-up or pull-down

resistor can be added to provide a valid input voltage during these times. The resistor value will depend on

multiple factors; however, a 10kΩ resistor is recommended and typically will meet all requirements.

7.3.3 Clamp Diode Structure

As shown in Figure 7-2, the inputs and outputs to this device have both positive and negative clamping diodes.

CAUTION

Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage

to the device. The input and output voltage ratings may be exceeded if the input and output clamp-

current ratings are observed.

GND

Logic

Input

Output

VCC

Device

-IIK

+IIK

+IOK

-IOK

Figure 7-2. Electrical Placement of Clamping Diodes for Each Input and Output

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CD74ACT157

SCHS340D – MARCH 2003 – REVISED JULY 2025

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