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L9800 датащи(PDF) 43 Page - STMicroelectronics |
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L9800 датащи(HTML) 43 Page - STMicroelectronics |
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43 / 55 page ![]() 11.5 SPI protocol The content of MOSI and MISO during SPI communication is shown in the Figure 34. MOSI line represents the frame sent from the MCU and the MISO line is the answer provided by the device. Figure 34. Relation between MOSI and MISO SI SO frame A frame B (previous response) response to frame A frame C response to frame B The SPI protocol provides the answer to a command frame only with the next transmission triggered by the MCU. 11.6 SPI frame structure 11.6.1 MOSI frame structure Each MOSI frame has 16 bits with the following structure: • A command bit R/W, ‘1’ for write, ‘0’ for read • 5 ADDRESS bits • 8 DATA bits • A PARITY bit, odd parity • A FR_CNT frame counter bit The frame count bit (FR_CNT) is toggled at each reception of the SPI data frame. For each frame, the microcontroller has to toggle this bit into the serial IN coherently with the internal device frame counter. If the device frame counter is not consistent with the one from the microcontroller, an SPI error is generated and the frame is rejected. The same behavior is expected for serial OUT. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W[15] ADDRESS[14:10] DATA[9:2] PAR[1] FR_CNT[0] 11.6.2 MISO frame structure Each MISO frame has 16 bits with the following structure: • An ERR error bit, ‘1’ if an error happened in the previous transmission, ‘0’ otherwise • 5 ADDRESS bits, for address feedback function • 8 DATA bits • A PARITY bit, odd parity • A FR_CNT frame counter bit The frame count bit (FR_CNT) is toggled at each reception of the SPI data frame. For each frame the microcontroller has to toggle this bit into the serial IN coherently with the internal device frame counter. If the device frame counter is not consistent with the one from the microcontroller, an SPI error is generated and the frame is rejected. The same behavior is expected for serial OUT. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ERR[15] ADDRESS[14:10] DATA[9:2] PAR[1] FR_CNT[0] 11.7 SPI registers The register banks are composed of 8-bit registers. L9800 Serial peripheral interface (SPI) DS14041 - Rev 2 page 43/55 |
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