L9800 datasheet(40/55 Pages) STMICROELECTRONICS

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Serial peripheral interface (SPI)

The SPI (serial peripheral interface) is a full duplex serial out of frame slave interface made of four lines SO, SI,

CLK and NCS. MOSI and MISO are the lines through which the data is transferred. Considering the out-of-frame

protocol implemented, it is important to ignore the first MISO received at the start of communication because it is

meaningless. The falling edge of NCS defines the start of the SPI frames. The L9800 samples the MOSI line (SI)

at the rising edge of CLK while the output data is shifted out on line MISO (SO) at the falling edge of CLK

(CPOL=’0’, CPHA = ‘0’). End of SPI access is defined by a rising edge of NCS.

The L9800 implements feature to guarantee that SPI frame is considered valid when at least 16 bits have been

transferred: in case of transaction with less than 16 bits is received, the frame will be discarded and ERR bit is

asserted in the next SPI frame. An SPI access with frame longer than 16 bits will not be discarded to allow daisy

chain operation.

Figure 30. SPI

11.1

SPI signal description

•

NCS-chip select

The system microcontroller selects the device by means of the NCS pin. Whenever the pin is in “low” state,

data transfer can take place. When NCS is in "high" state, any signals at the CLK and MOSI pins are

ignored and MISO is forced into a high-Z state.

•

NCS “high” to “low” transition

The requested information is transferred into the shift register.

If the device is in sleep mode, the MISO pin remains in high-Z state and no SPI transmission occurs.

•

NCS “low” to "high" transition

Data from the shift register is transferred into the addressed register.

•

CLK-serial clock

This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on

the rising edge of CLK while the serial output (SO) shifts diagnostic information out on the falling edge of

the serial clock. It is essential that the CLK pin is in “low” state whenever chip select NCS makes any

transition, otherwise the command is not accepted.

•

SI-serial input

Serial input data bits are shift-in at this pin, the most significant bit first. MOSI information is read on the

rising edge of SCLK. The input data consists of two parts, control bits and data bits.

•

SO-serial output

Data is shifted out serially at this pin, the most significant bit first. MISO is in high-Z state until the NCS pin

goes to “low” state. New data appears at the MISO pin following the falling edge of SCLK.

11.2

Daisy chain capability

L9800 implements SPI with daisy chain capability where a single master can address multiple slaves by driving a

single NCS and MOSI lines, getting back data from a single MISO line as reported in the Figure 31, in order to

build a chain. The end of the chain is connected to the output and input of the master device, MO, and MI

respectively. The master device provides the master clock MCLK, which is connected to the CLK line of each

device in the chain.

L9800

Serial peripheral interface (SPI)

DS14041 - Rev 2

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