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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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L9679E датащи(PDF) 4 Page - STMicroelectronics |
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L9679E датащи(HTML) 4 Page - STMicroelectronics |
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4 / 127 page  Pin name Pin function Min Max Unit CS_RS Remote SPI interface chip select -0.3 VCC+0.3 ≤ 6.5 V MOSI_RS Remote SPI interface data in -0.3 VCC+0.3 ≤ 6.5 V MISO_RS Remote SPI interface data out -0.3 VCC+0.3 ≤ 6.5 V VCC VCC voltage supply -0.3 6.5 V MISO_G Global SPI interface data out -0.3 VCC+0.3 ≤ 6.5 V MOSI_G Global SPI interface data in -0.3 VCC+0.3 ≤ 6.5 V SCLK_G Global SPI interface clock -0.3 VCC+0.3 ≤ 6.5 V CS_G Global SPI interface chip select -0.3 VCC+0.3 ≤ 6.5 V Exposed Pad Down Substrate ground - Squib/Pyroswitch ground -0.3 0.3 V Table 2. ESD robustness Symbol Parameter Test conditions Min Unit HBM HBM Human Body Model from Q100-002 All pins ±2000 V HBM HBM Human Body Model from Q100-002 Only for pins RSUx[x=0...3], SFx[x=0...7], SRx[x=0...7]. ±4000 V CDM CDM Charged Device Model from Q100-011 All pins ±500 V CDM CDM Charged Device Model from Q100-011 Corner pins ±750 V Table 3. Temperature ranges and thermal resistances Symbol Parameter Test conditions Min Typ Max Unit Tamb Operating ambient temperature -40 - 105 °C Tj Junction temperature -40 - 150 °C RTh j-case Thermal resistance junction-to-case Bottom cold plate in contact with package bottom case (e- pad side). JESD51 best practice guidelines. - 2.5 - °C/W RTh j-amb Thermal resistance junction-to- ambient With 2s2p PCB std Jedec. Natural convection. Standard Jedec best JESD51-7 - 30 - °C/W L9679E Absolute maximum ratings DS12485 - Rev 8 page 4/127 |
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