Startup Time Estimation

t

=

REF

1

f

REF

Time(s)

2.27V

2.64V

t

pul

t

puh

t

rsu

t

delay

t

VCO_CAL

t

PLL_LOCK

Powerup

Reference

Startup

Delay

VCOCalibration

PLLLock

CDCE421A

SCAS873 – APRIL 2009..................................................................................................................................................................................................... www.ti.com

The startup time for the CDCE421A can be estimated based on the parameters defined in Table 16 and

illustrated in Figure 11.

Based on these parameters, the CDCE421A startup time limits tMAX and tMIN can be calculated as shown in these

equations:

tMAX = tpuh + trsu + tdelay + tVCO_CAL + tPLL_LOCK

tMIN = tpul + trsu + tdelay + tVCO_CAL + tPLL_LOCK

Table 16. Timing Definitions: Startup Time Dependencies

Parameter

Definition

Description

Formula/Method of Determination

The reciprocal of the applied reference

tREF

Reference Clock Period

frequency (in seconds).

Power-Up Time (low

Power-supply rise time to low limit of Power

Time required for Power Supply to

tpul

limit)

On Reset (POR) trip point.

ramp to 2.27 V.

Power-Up Time (high

Power-supply rise time to high limit of POR

Time required for Power Supply to

tpuh

limit)

trip point.

ramp to 2.64 V.

After POR releases, the Colpits oscillator is

enabled. This startup time is required for the

Best case: 500

µs

trsu

Reference Startup Time

oscillator to generate the requisite signal

Worst case: 800

µs (for a crystal input)

levels for the delay block to be clocked by

0 s (for an LVCMOS input)

the reference input.

Internal delay time generated from the

tdelay

Delay Time

reference clock. This delay provides time for

tdelay = 16384 × tREF

the reference oscillator to stabilize.

VCO Calibration Time generated from the

reference clock. This process selects the

tVCO_CAL

VCO Calibration Time

tVCO_CAL = 550 × tREF

operating point for the VCO based on the

PLL settings.

Time required for PLL to lock within ±10 ppm Based on the 400-kHz loop bandwidth,

tPLL_LOCK

PLL Lock Time

of fREF.

the PLL will settle in 5

τ or 12.5 µs.

Figure 11. Startup Time Dependencies

20

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