AMC7836IPAPR datasheet(47/91 Pages) TI2

47 / 91 page

AMC7836

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SLAS986D – NOVEMBER 2014 – REVISED FEBRUARY 2018

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Table 8. Register Map (continued)

ADDRESS

TYPE

DEFAULT

0x63

R/W

DACC9-Data (High Byte)

0x64

R/W

DACC10-Data (Low Byte)

0x65

R/W

DACC10-Data (High Byte)

0x66

R/W

DACC11-Data (Low Byte)

0x67

R/W

DACC11-Data (High Byte)

0x68

R/W

DACD12-Data (Low Byte)

0x69

R/W

DACD12-Data (High Byte)

0x6A

R/W

DACD13-Data (Low Byte)

0x6B

R/W

DACD13-Data (High Byte)

0x6C

R/W

DACD14-Data (Low Byte)

0x6D

R/W

DACD14-Data (High Byte)

0x6E

R/W

DACD15-Data (Low Byte)

0x6F

R/W

DACD15-Data (High Byte)

0x70

Alarm Status 0

0x71

Alarm Status 1

0x72

General Status

0x73 - 0x79

—

Reserved

0x7A

R/W

GPIO

0x7B - 0x7F

—

Reserved

0x80

R/W

ADC16-Upper-Thresh (Low Byte)

0x81

R/W

ADC16-Upper-Thresh (High Byte)

0x82

R/W

ADC16-Lower-Thresh (Low Byte)

0x83

R/W

ADC16-Lower-Thresh (High Byte)

0x84

R/W

ADC17-Upper-Thresh (Low Byte)

0x85

R/W

ADC17-Upper-Thresh (High Byte)

0x86

R/W

ADC17-Lower-Thresh (Low Byte)

0x87

R/W

ADC17-Lower-Thresh (High Byte)

0x88

R/W

ADC18-Upper-Thresh (Low Byte)

0x89

R/W

ADC18-Upper-Thresh (High Byte)

0x8A

R/W

ADC18-Lower-Thresh (Low Byte)

0x8B

R/W

ADC18-Lower-Thresh (High Byte)

0x8C

R/W

ADC19-Upper-Thresh (Low Byte)

0x8D

R/W

ADC19-Upper-Thresh (High Byte)

0x8E

R/W

ADC19-Lower-Thresh (Low Byte)

0x8F

R/W

ADC19-Lower-Thresh (High Byte)

0x90

R/W

ADC20-Upper-Thresh (Low Byte)

0x91

R/W

ADC20-Upper-Thresh (High Byte)

0x92

R/W

ADC20-Lower-Thresh (Low Byte)

0x93

R/W

ADC20-Lower-Thresh (High Byte)

0x94

R/W

LT-Upper-Thresh (Low Byte)

0x95

R/W

LT-Upper-Thresh (High Byte)

0x96

R/W

LT-Lower-Thresh (Low Byte)

0x97

R/W

LT-Lower-Thresh (High Byte)

0x98 - 0x9F

—

Reserved

0xA0

R/W

ADC16-Hysteresis

0xA1

R/W

ADC17-Hysteresis

0xA2

R/W

ADC18-Hysteresis

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