LP8754 datasheet(12/52 Pages) TI2

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LP8754

SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014

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2C Serial Bus Timing Parameters (continued)

Serial bus address is selected by the ADDR pin. Connect the pin to GND (addr = 60h), VIOSYS (addr = 61h), SDASYS (addr

= 62h), or SCLSYS (addr = 63h). Both of the serial buses share the same address; that is, if addr = 60h is selected for the

System bus, the Dynamic Voltage Scaling bus will respond to the same address. Start conditions are used to secure the I

slave address. During the I

2C bus start condition, it is detected whether the ADDR is connected to SDASYS, SCLSYS, GND,

or VIOSYS. The I

2C host should allow at least 500 µs before sending data to the LP8754 after the rising edge of the VIOSYS

line.

These specifications are ensured by design. Limits apply over the full ambient temperature range -40°C

≤ TA ≤ 85°C, VVDDA5V

= VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V, (unless otherwise noted).

SYMBOL

PARAMETER (See Figure 1)

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Standard mode

4.7

µs

Set-up time for a repeated

tSU;STA

Fast mode

0.6

start condition

High-speed mode

160

Standard mode

4.0

µs

Hold time for a start or a

tHD;STA

Fast mode

0.6

repeated start condition

High-speed mode

160

Standard mode

4.7

Bus free time between a stop

tBUF

µs

and start condition

Fast mode

1.3

Standard mode

4.0

µs

Set-up time for a stop

tSU;STO

Fast mode

0.6

condition

High-speed mode

160

Standard mode

1000

Fast mode

300

trDA

Rise time of SDA signal

High-speed mode, Cb = 100 pF (max)

High-speed mode, Cb = 400 pF (max)

(4)

160

Standard mode

300

Fast Mode

6.5

300

tfDA

Fall time of SDA signal

High-speed mode, Cb = 100 pF (max)

High-speed mode, Cb = 400 pF (max)

(4)

160

Standard mode

1000

Fast mode

300

trCL

Rise time of SCL signal

High-speed mode, Cb = 100 pF (max)

High-speed mode, Cb = 400 pF (max)

(5)

Rise time of SCL signal after

High-speed mode, Cb = 100 pF (max)

trCL1

a repeated start condition and

High-speed mode, Cb = 400 pF (max)

(5)

160

after anacknowledge bit

Standard mode

300

Fast mode

6.5

300

tfCL

Fall time of a SCL signal

High-speed mode, Cb = 100 pF (max)

High-speed mode, Cb = 400 pF (max)

(5)

Capacitive load for each bus

400

line (SCL and SDA)

Fast mode

Pulse width of spike

tSP

suppressed(6)

High-speed mode

(5)

For bus line loads Cb between 100 pF and 400 pF the timing parameters must be linearly interpolated.

(6)

Spike suppression filtering on SCLSYS, SCLSR, SDASYS and SDASR will suppress spikes that are less than the indicated width.

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