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LP8754 датащи(PDF) 33 Page - Texas Instruments |
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LP8754 датащи(HTML) 33 Page - Texas Instruments |
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33 / 52 page ![]() LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 D7 D6 D5 D4 D3 D2 D1 D0 Reserved EN_SS Reserved DIS_DIF_B0 Reserved SLP_POL LP_EN Bits Field Type Default Description 7:6 Reserved R/W 00 5 EN_SS R/W 0 Spread Spectrum 1 = Spread Spectrum enabled 0 = Spread Spectrum disabled 4 Reserved R/W 0 3 DIS_DIF_B0 R/W 0 Disable Differential-to-single-ended amplifier 1 = Differential amplifier disabled 0 = Differential amplifier enabled 2 Reserved R/W 0 1 SLP_POL R/W 0 Sets the polarity of the NSLP pin 1 = NSLP is active high 0 = NSLP is active low 0 LP_EN R/W 1 1 = allows Low-Power PFM mode. In order to reduce power consumption under low load conditions, the unit will automatically switch off unused internal blocks. 0 = Low-Power mode not allowed 7.6.14 RESET Address: 0x11 D7 D6 D5 D4 D3 D2 D1 D0 Reserved SW_RESET Bits Field Type Default Description 7:1 Reserved R/W 000 0000 0 SW_RESET R/W 0 Writing this bit with '1' and '0', in this order, will reset the registers to the default values. If NRST is still kept HIGH, the converter output(s) will be regulated to the programmed register values. If a full POR reset is required VVIOSYS must be pulled low. The fault flags are persistent over SW-reset. 7.6.15 DELAY_BUCK0 Address: 0x12 D7 D6 D5 D4 D3 D2 D1 D0 DELAY_B0 Bits Field Type Default Description 7:0 DELAY_B0 R/W 0000 0000 Master delay Sets the delay time from when NRST is asserted to when the VOUT rail is enabled. Sets the delay time from when NRST is de-asserted to when the VOUT rail is disabled. DELAY = DELAY_B0 * 100 µs If DELAY_B0 = FFh, supply is never enabled. (1) (1) If this register is set to FFh when the converter is already started, it will cause an immediate power down of the converter. 7.6.16 CHIP_ID Address: 0x18 D7 D6 D5 D4 D3 D2 D1 D0 DEVICE OTP_REV DIE_REV Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 33 Product Folder Links: LP8754 |
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