LP8754

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SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014

6-Phase Buck System Characteristics (continued)

Limits apply over the full ambient temperature range -40°C

≤ TA ≤ 85°C, VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V,

VOUT = 1.1 V, (unless otherwise noted).

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Average output current, Programmable via control

register, VOUT = 1.1 V

(2)

PFM_ENTRY_B0[2:0] = 000

100

PWM-to-PFM switchover current

PFM_ENTRY_B0[2:0] = 001

125

IPWM–PFM

mA

threshold

PFM_ENTRY_B0[2:0] = 010

150

PFM_ENTRY_B0[2:0] = 011

175

PFM_ENTRY_B0[2:0] = 100

225

ADD_PH_B0[2:0] = 010

500

ADD_PH_B0[2:0] = 011

600

ADD_PH_B0[2:0] = 100

700

IADD

Phase adding level

mA

ADD_PH_B0[2:0] = 101

800

ADD_PH_B0[2:0] = 110

900

ADD_PH_B0[2:0] = 111

1000

SHED_PH_B0[2:0] = 000

300

SHED_PH_B0[2:0] = 001

400

SHED_PH_B0[2:0] = 010

500

ISHED

Phase shedding level

mA

SHED_PH_B0[2:0] = 011

600

SHED_PH_B0[2:0] = 100

700

SHED_PH_B0[2:0] = 101

800

2.5 V

≤ VVINBXX ≤ 5 V

Line Regulation

0.05

%/V

ILOAD = 1 A, forced PWM

Load regulation in PWM mode of

100 mA

≤ ILOAD ≤ 10 A, Differential sensing

0.2

%/A

operation

enabled

AUTO (no Low-Power PFM) mode, IOUT 0.5 mA →

±30

mV

500 mA

→ 0.5 mA, 100 ns load step

ΔVOUT

PWM mode, IOUT 0.6 A → 2 A → 0.6 A, 400-ns

Transient load step response

±20

mV

load step

PWM mode, IOUT 1 A → 8 A → 1 A, 400-ns load

±60

mV

step

VVINBXX stepping 3.3 V <—> 3.8 V, tr = tf = 10 µs,

Transient line response

±15

mV

IOUT = 2000 mA DC

DC load each phase

1670

IOUT

Output current

mA

Six phases combined(3)

10000

Effective capacitance during operation, VOUT = 0.6

COUT

Output capacitance(4)

30

50

µF

V to 1.67 V, Min value over TA –40°C to 85°C

(3)

The power switches in the LP8754 are designed to operate continuously with currents up to the switch current limit thresholds. However,

when continuously operating at high current levels there will be significant heat generated within the IC and thus sustained total DC

current which the device can support is typically limited by thermal constraints. Thermal issues will become extremely important when

designing PCB and the thermal environment of the LP8754. PCB with high thermal efficiency is required to ensure the junction

temperature is kept below 125°C. Completing thermal analyses in early stages of the product design process is highly recommended to

predict thermal performance at board level. Under high current load conditions the serial bus master device must monitor the

temperature of the converter using the Thermal warning feature, see Protection Features Characteristics. If the 2nd thermal warning is

triggered at 120°C, the application must quickly decrease the load current to keep the converter within its recommended operating

temperature.

(4)

Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. The performance of the LP8754 device

depends greatly on the care taken in designing the Printed Circuit Board (PCB). The use of low inductance and low serial resistance

ceramic capacitors is strongly recommended, while proper grounding is crucial. Attention should be given to decoupling the power

supplies. Decoupling capacitors must be connected close to the IC and between the power and ground pins to support high peak

currents being drawn from System Power Rail during turn-on of the switching MOSFETs. Keep input and output traces as short as

possible, because trace inductance, resistance and capacitance can easily become the performance limiting items.

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