INA110 datasheet(9/22 Pages) TI2

9 / 22 page

INA110

SBOS147A

www.ti.com

GAIN SELECTION

Gain selection is accomplished by connecting the appropri-

ate pins together on the INA110. Table I shows possible

gains from the internal resistors. Keep the connections as

short as possible to maintain accuracy.

Gains other than 1, 10, 100, 200, and 500 can be set by

adding an external resistor, RG, between pin 3 and pins 12,

16, and 11. Gain accuracy is a function of RG and the

internal resistors which have a

±20% tolerance with

20ppm/

°C drift. The equation for choosing R

G is shown

below.

Gain can also be changed in the output stage by adding

resistance to the feedback loop shown in Figure 4. This is

useful for increasing the total gain or reducing the input

stage gain to prevent saturation of input amplifiers.

The output gain can be changed as shown in Table II.

Matching of R1 and R3 is required to maintain high CMR. R2

sets the gain with no effect on CMR.

CONNECT PIN 3

GAIN

TO PIN

ACCURACY (%)

DRIFT (ppm/

°C)

The following gains have assured accuracy:

none

0.02

0.05

100

0.1

200

0.2

500

0.5

The following gains have typical accuracy as shown:

300

12, 16

0.25

600

11, 12

0.25

700

11, 16

800

11, 12, 16

TABLE I. Internal Gain Connections.

are eliminated since they are inside the feedback loop.

Proper connection is shown in Figure 1. When more current

is to be supplied, a power booster can be placed within the

feedback loop as shown in Figure 5. Buffer errors are

minimized by the loop gain of the output amplifier.

FIGURE 4. Gain Adjustment of Output Stage Using H Pad

Attenuator.

FIGURE 5. Current Boosting the Output.

3553

INA110

OUT

∆V

L = 100mA

Sense

G –1

40k

Ω

G =

– 50

Ω

OUTPUT STAGE GAIN

R1 AND R3

21.2k

Ω

2.74k

Ω

51k

Ω

511

Ω

1.5k

Ω

340

Ω

TABLE II. Output Stage Gain Control.

COMMON-MODE INPUT RANGE

It is important not to exceed the input amplifiers’ dynamic

range (see Typical Characteristics). The differential input

signal and its associated common-mode voltage should not

cause the output of A1 and A2 (input amplifiers) to exceed

approximately

±10V with ±15V supplies or nonlinear opera-

tion will result. Such large common-mode voltages, when

the INA110 is in high gain, can cause saturation of the input

stage even though the differential input is very small. This

can be avoided by reducing the input stage gain and increas-

ing the output stage gain with an H pad attenuator (see

Figure 4).

OUTPUT SENSE

An output sense has been provided to allow greater accuracy

in connecting the load. By attaching this feedback point to

the load at the load site, IR drops due to load currents that

LOW BIAS CURRENT

OF FET INPUT ELIMINATES DC ERRORS

Because the INA110 has FET inputs, bias currents drawn

through input source resistors have a negligible effect on DC

accuracy. The picoamp levels produce no more than micro-

volts through megohm sources. Thus, input filtering and

input series protection are readily achievable.

A return path for the input bias currents must always be

provided to prevent charging of stray capacitance. Other-

wise, the output can wander and saturate. A 1M

Ω to 10MΩ

resistor from the input to common will return floating

sources such as transformers, thermocouples, and

AC-coupled inputs (see Applications section).

DYNAMIC PERFORMANCE

The INA110 is a fast-settling FET input instrumentation

amplifier. Therefore, careful attention to minimize stray

capacitance is necessary to achieve specified performance.

High source resistance will interact with input capacitance to

reduce the overall bandwidth. Also, to maintain stability,

avoid capacitance from the output to the gain set, offset

adjust, and input pins.

Applications with balanced-source impedance will provide

the best performance. In some applications, mismatched

source impedances may be required. If the impedance in the

INA110

OUT

∆V

Output Stage Gain

2 || 20kΩ) + R1 + R3

2 || 20kΩ

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