INA110 datasheet(8/22 Pages) TI2

8 / 22 page

INA110

SBOS147A

www.ti.com

DISCUSSION OF

PERFORMANCE

A simplified diagram of the INA110 is shown on the first

page. The design consists of the classical three operational

amplifier configuration using current-feedback type op amps

with precision FET buffers on the input. The result is an

instrumentation amplifier with premium performance not

normally found in integrated circuits.

The input section (A1 and A2) incorporates high perfor-

mance, low bias current, and low drift amplifier circuitry.

The amplifiers are connected in the noninverting configura-

tion to provide high input impedance (1012

Ω). Laser-trim-

ming is used to achieve low offset voltage. Input cascoding

assures low bias current and high CMR. Thin-film resistors

on the integrated circuit provide excellent gain accuracy and

temperature stability.

The output section (A3) is connected in a unity-gain differ-

ence amplifier configuration. Precision matching of the four

10kΩ resistors, especially over temperature and time,

assures high common-mode rejection.

BASIC POWER SUPPLY

AND SIGNAL CONNECTIONS

Figure 1 shows the proper connections for power supply and

signal. Supplies should be decoupled with 1

µF tantalum

capacitors as close to the amplifier as possible. To avoid

gain and CMR errors introduced by the external circuit,

connect grounds as indicated, being sure to minimize ground

resistance. Resistance in series with the reference (pin 6)

will degrade CMR. To maintain stability, avoid capacitance

from the output to the gain set, offset adjust, and input pins.

INA110’s input (RTI) is the offset of the input stage plus

the offset of the output stage divided by the gain of the

input stage. This allows specification of offset independent

of gain.

FIGURE 2. Offset Adjustment Circuit.

INA110

OUT

100k

Ω

–V

100k

Ω

Input

Offset

Adjust

Output

Offset

Adjust

∆V

For systems using computer autozeroing techniques, neither

offset nor offset drift are of concern. In many other applica-

tions, the factory-trimmed offset gives excellent results.

When greater accuracy is desired, one adjustment is usually

sufficient. In high gains (>100) adjust only the input offset,

and in low gains the output offset. For higher precision in all

gains, both can be adjusted by first selecting high gain and

adjusting input offset and then low gain and adjusting output

offset. The offset adjustment will, however, add to the drift

by approximately 0.33

µV/°C per 100µV of input offset

voltage that is adjusted. Therefore, care should be taken

when considering use of adjustment.

Output offsetting can be accomplished as shown in Figure 3

by applying a voltage to the reference (pin 6) through a

buffer. This limits the resistance in series with pin 6 to

minimize CMR error. Be certain to keep this resistance low.

Note that the offset error can be adjusted at this reference

point with no appreciable degradation in offset drift.

FIGURE 3. Output Offsetting.

INA110

OUT

OPA177

∆V

OUT = VOFFSETTING + ∆VIN G.

–V

OFFSETTING

With ±V

CC = 15V, R1 = 100kΩ, R2 = 1MΩ.

3 = 10kΩ, VOFFSETTING = ±150mV.

OFFSET ADJUSTMENT

Figure 2 shows the offset adjustment circuit for the INA110.

Both the offset of the input stage and output stage can be

adjusted separately. Notice that the offset referred to the

FIGURE 1. Basic Circuit Connection.

OUT

∆V

x10

x100

x200

x500

1µF

–V

1µF

Sense

OUT = ∆VIN G

INA110

INA110 датащи(PDF) 8 Page - Texas Instruments

INA110 датащи(HTML) 8 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

датащи скачать

ссылки URL