CDCE706

www.ti.com ........................................................................................................................................... SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008

DEVICE CHARACTERISTICS (continued)

over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

All PLLs

80

200

Normal speed-mode(3)

VCO frequency of internal PLL (any of three

fVCO

PLL2 with SSC

80

167

MHz

PLLs)

High-speed mode(3)

180

300

VCC = 2.5 V

250

LVCMOS output frequency range(4), See

fOUT

MHz

Figure 4

VCC = 3.3 V

300

LVCMOS PARAMETER

VIK

LVCMOS input voltage

VCC = 3 V, II = –18 mA

–1.2

V

LVCMOS input current (CLK_IN0 and

II

VI = 0 V or VCC, VCC = 3.6 V

±5

µA

CLK_IN1)

IIH

LVCMOS input current (S1/S0)

VI = VCC, VCC = 3.6 V

5

µA

IIL

LVCMOS input current (S1/S0)

VI = 0 V, VCC = 3.6 V

–35

–10

µA

Input capacitance at CLK_IN0 and

CI

VI = 0 V or VCC

3

pF

CLK_IN1

LVCMOS PARAMETER FOR VCCOUT = 3.3-V Mode

VCCOUT = 3 V, IOH = –0.1 mA

2.9

VOH

LVCMOS high-level output voltage

VCCOUT = 3 V, IOH = –4 mA

2.4

V

VCCOUT = 3 V, IOH = –6 mA

2.1

VCCOUT = 3 V, IOL = 0.1 mA

0.1

VOL

LVCMOS low-level output voltage

VCCOUT = 3 V, IOL = 4 mA

0.5

V

VCCOUT = 3 V, IOL = 6 mA

0.85

All PLL bypass

9

tPLH,

Propagation delay

ns

tPHL

VCO bypass

11

tr0/tf0

Rise and fall time for output slew rate 0

VCCOUT = 3.3 V (20%–80%)

1.7

3.3

4.8

ns

tr1/tf1

Rise and fall time for output slew rate 1

VCCOUT = 3.3 V (20%–80%)

1.5

2.5

3.2

ns

tr2/tf2

Rise and fall time for output slew rate 2

VCCOUT = 3.3 V (20%–80%)

1.2

1.6

2.1

ns

Rise and fall time for output slew rate 3

tr3/tf3

VCCOUT = 3.3 V (20%–80%)

0.4

0.6

1

ns

(default configuration)

fOUT = 50 MHz

55

90

1 PLL, 1 output

fOUT = 245.76 MHz

45

80

tjit(cc)

Cycle-to-cycle jitter(5)(6)

ps

fOUT = 50 MHz

125

155

3 PLLs, 3 outputs

fOUT = 245.76 MHz

60

95

fOUT = 50 MHz

60

90

1 PLL, 1 output

fOUT = 245.76 MHz

55

80

tjit(per)

Peak-to-peak period jitter(5)(6)

ps

fOUT = 50 MHz

145

180

3 PLLs, 3 outputs

fOUT = 245.76 MHz

70

105

1.6-ns rise/fall time at fVCO = 150 MHz,

tsk(o)

Output skew (see(7) and Table 5)

200

ps

Pdiv = 3

odc

Output duty cycle(8)

fVCO = 100 MHz, Pdiv = 1

45%

55%

(3)

Normal-speed mode or high-speed mode must be selected by the VCO frequency selection bit in byte 6, bits [7:5]. The minimum fVCO

can be lower, but impacts jitter performance.

(4)

Do not exceed the maximum power dissipation of the 20-pin TSSOP package (600 mW at no air flow).

(5)

50,000 cycles

(6)

Jitter depends on configuration. Jitter data is normal tr/tf, input frequency = 3.84 MHz, fVCO = 245.76 MHz.

(7)

The tsk(o) specification is only valid for equal loading of all outputs.

(8)

odc depends on output rise and fall time (tr/tf). The data is for normal tr/tf and is valid for both SSC on and off.

Copyright © 2005–2008, Texas Instruments Incorporated

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