ADS7828-Q1

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SBAS456B – DECEMBER 2008 – REVISED JANUARY 2016

Feature Description (continued)

Figure 14 shows how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two

types of data transfer are possible:

•

Data transfer from a master transmitter to a slave receiver.

The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave

returns an acknowledge bit after the slave address and each received byte.

•

Data transfer from a slave transmitter to a master receiver.

The first byte, the slave address, is transmitted by the master. The slave then returns an acknowledge bit.

Next, a number of data bytes are transmitted by the slave to the master. The master returns an acknowledge

bit after all received bytes other than the last byte. At the end of the last received byte, a not-acknowledge is

returned.

The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended

with a Stop condition or a repeated Start condition. Since a repeated Start condition is also the beginning of the

next serial transfer, the bus will not be released.

7.4 Device Functional Modes

The ADS7828 may operate in the following two modes:

•

Slave Receiver Mode

Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is

transmitted. Start and Stop conditions are recognized as the beginning and end of a serial transfer. Address

recognition is performed by hardware after reception of the slave address and direction bit.

•

Slave Transmitter Mode

The first byte (the slave address) is received and handled as in the slave receiver mode. However, in this

mode the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted on SDA by

the ADS7828 while the serial clock is input on SCL. Start and Stop conditions are recognized as the

beginning and end of a serial transfer.

7.4.1 Address Byte

The address byte is the first byte received following the Start condition from the master device (see Figure 15).

The first five bits (MSBs) of the slave address are factory pre-set to 10010. The next two bits of the address byte

are the device select bits, A1 and A0. Input pins (A1-A0) on the ADS7828 determine these two bits of the device

address for a particular ADS7828. A maximum of four devices with the same pre-set code can therefore be

connected on the same bus at one time.

Figure 15. Address Byte

MSB

6

5

4

3

2

1

LSB

1

0

0

1

0

A1

A0

R/W

The A1 and A0 address inputs can be connected to VDD or digital ground. The device address is set by the state

of these pins upon power-up.

The last bit of the address byte (R/W) defines the operation to be performed. When set to a 1, a read operation is

selected; when set to a 0, a write operation is selected. Following the Start condition, the ADS7828 monitors the

SDA bus, checking the device type identifier being transmitted. Upon receiving the 10010 code, the appropriate

device select bits, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line.

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