SAR

2.5-V V

REF

Serial

Interface

SDA

Comparator

S/H Amp

REF

IN

OUT

/REF

SCL

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

A0

A1

CDAC

8-Channel

Multiplexer

Buffer

ADS7828-Q1

www.ti.com

SBAS456B – DECEMBER 2008 – REVISED JANUARY 2016

7 Detailed Description

7.1 Overview

The ADS7828 is a classic Successive Approximation Register (SAR) ADC. The architecture is based on

capacitive redistribution which inherently includes a sample-and-hold function. The converter is fabricated on a

0.6

μ CMOS process.

The ADS7828 core is controlled by an internally generated free-running clock. When the ADS7828 is not

performing conversions or being addressed, it keeps the ADC core powered off, and the internal clock does not

operate.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Analog Input

When the converter enters the hold mode, the voltage on the selected CHx pin is captured on the internal

capacitor array. The input current on the analog inputs depends on the conversion rate of the device. During the

sample period, the source must charge the internal sampling capacitor (typically 25 pF). After the capacitor has

been fully charged, there is no further input current. The amount of charge transfer from the analog source to the

converter is a function of conversion rate.

7.3.2 Reference

The ADS7828 can operate with an internal 2.5-V reference or an external reference. If a 5-V supply is used, an

external 5-V reference is required in order to provide full dynamic range for a 0 V to +VDD analog input. This

external reference can be as low as 50 mV. When using a 2.7-V supply, the internal 2.5-V reference will provide

full dynamic range for a 0 V to +VDD analog input.

As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is

often referred to as the LSB (least significant bit) size and is equal to the reference voltage divided by 4096. This

means that any offset or gain error inherent in the ADC will appear to increase, in terms of LSB size, as the

reference voltage is reduced.

The noise inherent in the converter will also appear to increase with lower LSB size. With a 2.5-V reference, the

internal noise of the converter typically contributes only 0.32 LSB peak-to-peak of potential error to the output

code. When the external reference is 50 mV, the potential error contribution from the internal noise is 50 times

larger—16 LSBs. The errors due to the internal noise are Gaussian in nature and can be reduced by averaging

consecutive conversion results.

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