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CLOCK INPUT

5 kW

5 kW

3 pF

3 pF

6 pF

CLKP

CLKM

CM

CM

0.01mF

0.01mF

CLKP

CLKM

Square Wave

or Sine Wave

(3V

PP)

ADS5542

0.01mF

CLKP

CLKM

0.01mF

Differential Square Wave

or Sine Wave

(3V

PP)

ADS5542

ADS5542

SBAS308D – MAY 2004 – REVISED FEBRUARY 2007

The ADS5542 clock input can be driven with either a differential clock signal or a single-ended clock input, with

little or no difference in performance between both configurations. The common-mode voltage of the clock inputs

is set internally to CM (pin 17) using internal 5-k

Ω resistors that connect CLKP (pin 10) and CLKM (pin 11) to

CM (pin 17), as shown in Figure 43.

Figure 43. Clock Inputs

When driven with a single-ended CMOS clock input, it is best to connect CLKM (pin 11) to ground with a

0.01-

µF capacitor, while CLKP is ac-coupled with a 0.01-µF capacitor to the clock source, as shown in

Figure 44.

Figure 44. AC-Coupled, Single-Ended Clock Input

The ADS5542 clock input can also be driven differentially, reducing susceptibility to common-mode noise. In this

case, it is best to connect both clock inputs to the differential input clock signal with 0.01-

µF capacitors, as

shown in Figure 45.

Figure 45. AC-Coupled, Differential Clock Input

For high input frequency sampling, it is recommended to use a clock source with low jitter. Additionally, the

internal ADC core uses both edges of the clock for the conversion process. This means that, ideally, a 50% duty

cycle should be provided. Figure 46 shows the performance variation of the ADC versus clock duty cycle.

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