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APPLICATION INFORMATION

THEORY OF OPERATION

INPUT CONFIGURATION

R

3

R

1a

L

1

L

2

R

1b

C

1a

C

1b

C

A

CP

1

CP

3

VINCM

1V

CP

4

CP

2

INP

INM

S3a

S3b

S2

S1a

S1b

L1, L2: 6 nH − 10 nH effective

R1a, R1b: 5W − 8W

C1a, C1b: 2.2 pF − 2.6 pF

CP1, CP2: 2.5 pF − 3.5 pF

CP3, CP4: 1.2 pF − 1.8 pF

CA: 0.8 pF − 1.2 pF

R3: 80 W − 120 W

Swithches: S1a, S1b: On Resistance: 35 W − 50 W

S2: On Resistance: 7.5 W − 15 W

S3a, S3b: On Resistance: 40 W − 60 W

All switches OFF Resistance: 10 GW

ADS5542

SBAS308D – MAY 2004 – REVISED FEBRUARY 2007

The ADS5542 is a low-power, 14-bit, 80 MSPS, CMOS, switched capacitor, pipeline ADC that operates from a

single 3.3-V supply. The conversion process is initiated by a falling edge of the external input clock. Once the

signal is captured by the input S&H, the input sample is sequentially converted by a series of small resolution

stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edges

are used to propagate the sample through the pipeline every half clock cycle. This process results in a

datalatency of 17.5 clock cycles, after which the output data is available as a 14-bit parallel word, coded in either

straight offset binary or binary two's complement format.

The analog input for the ADS5542 consists of a differential sample-and-hold architecture implemented using the

switched capacitor technique shown in Figure 37.

A.

All Switches are ON in sampling phase which is approximately one half of a clock period.

Figure 37. Analog Input Stage

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