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Reference Input Voltage (VREF)

Power Supply (AVDD, AVSS, DVDD)

SERIAL INTERFACE

DAC8580

SLAS458B – JUNE 2005 – REVISED AUGUST 2005

THEORY OF OPERATION (continued)

On power up, a switching circuitry is used to lower power-on transients. Before power up, the DAC output is

connected to AGND voltage using a 100-k

Ω resistor. During power up, transient output voltages are typically less

than 200 mV. Approximately 30 µs after power up, the output gets set to mid-scale value (power-on reset). This

mid-scale value is around AGND potential within offset error limits.

Table 1. Two's-Complement Data Format

DAC OUTPUT

DIGITAL CODE

BINARY

HEX

+Vref

0111111111111111

7FFF

+Vref/2

0100000000000000

4FFF

0

0000000000000000

0000

–Vref/2

1011111111111111

BFFF

–Vref

1000000000000000

8000

The reference input pin VREF is typically tied to a standard 3-V, 4.096-V, or 5-V external reference. Minimum

external reference voltage that can be used is 3 V. A 0.1-µF (or less) bypass capacitor is recommended,

depending on the load-driving capability of the external voltage reference. To reduce crosstalk and improve

settling time, VREF pin is internally buffered by a high-performance amplifier. Pin VREF has a constant 5-kΩ

impedance to AGND; therefore, a reference driver should be chosen with care. Because the VREF pin does not

induce glitches, multiple DAC8580 devices can share a single external reference without crosstalk concerns. In

addition, because the reference pin does not require fast current spikes, the reference voltage generator can be

heavily filtered to improve noise performance without hurting settling or distortion. The output range of the

DAC8580 is equal to ±VREF. Pin VREF should not be powered before the supply pins. REF3133 and REF3140 are

recommended to set the DAC8580 output range to ±3.3 V and ±4.096 V, respectively. The reference bandwidth

is 10 MHz (small signal) and 3 MHz (large signal).

The DAC8580 uses ±5-V analog power supplies (AVDD, AVSS) and a 1.8-V to 5.5-V digital supply (DVDD). Analog

and digital ground pins (AGND and DGND) are also provided. For low-noise operation, analog and digital power,

and ground pins should be separated. Sufficient bypass capacitors, at least 1 µF, should be placed between

AVDD and AVSS, AVSS and DGND, and DVDD and DGND pins. Series inductors are not recommended on the

supply paths. AVDD, DVDD, AVSS, and VREF should be applied together. VREF must not be applied before AVDD

and AVSS. During power up, all digital inputs and the reference input should be kept at zero volts. If any pin is

brought high before the power supplies, overvoltage protection circuitry turns on.

The DAC8580 serial interface consists of serial data input pin SDIN, bit clock pin SCLK, and word clock pin

FSYNC. The serial interface is designed to support the right-justified (mono) audio format. The serial inputs are

1.8-V to 5.5-V logic compatible.

Data from SDIN pin is continuously clocked into a 16-bit shift register, at each rising edge of SCLK. Falling edge

of the FSYNC latches the shift register data into a 16-bit temporary register. The second rising edge of SCLK

following the falling edge of FSYNC transfers the data stored in the temporary register to the DAC latch when the

digital filter is turned off; when the digital filter is on, data is transferred to the digital filter. That is, DAC data is

updated 1.5 clock cycles after the falling edge of FSYNC when the digital filter is off. The shift register

continuously performs a shift operation; therefore, on the falling edge of the word clock FSYNC, the last 16 bits

received determines the data update (right-justified). Data is received MSB-first. This operation provides a

simplified timing for the digital filter, and enables clock rates exceeding 30 MHz. See the timing diagram for

details.

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Not Recommended For New Designs