AM486DE2 datasheet(16/52 Pages) AMD

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Am486DE2 Microprocessor

SMIACT (New)

SMM Interrupt Active (Active-Low Output)

SMIACT goes Low in response to SMI. It indicates that

the processor is operating under SMM control. SMIACT

remains Low until the processor receives a RESET sig-

nal or executes the Resume instruction (RSM) to leave

SMM. This signal is always driven. It does not float dur-

ing bus HOLD or BOFF.

Note: Do not use SRESET to exit from SMM. The sys-

tem should block SRESET during SMM.

SRESET (New)

Soft Reset (Input)

The CPU samples SRESET on every rising clock edge.

If SRESET is sampled active, the SRESET sequence

begins on the next instruction boundary. SRESET

resets the processor, but, unlike RESET, does not

cause it to sample UP or WB/WT, or affect the FPU,

cache, CD and NW bits in CR0, and SMBASE. SRESET

is asynchronous and must meet the same timing as

RESET.

STPCLK (New)

Stop Clock (Active-Low Input)

A Low input signal indicates a request has been made

to turn off the CLK input. When the CPU recognizes a

STPCLK, the processor:

s stops execution on the next instruction boundary

(unless superseded by a higher priority interrupt)

s empties all internal pipelines and write buffers

s generates a Stop Grant acknowledge bus cycle

STPCLK is active Low and has an internal pull-up resis-

tor. STPCLK is asynchronous, but it must meet setup

and hold times t20 and t21 to ensure recognition in any

specific clock. STPCLK must remain active until the

Stop Clock special bus cycle is issued and the system

returns either RDY or BRDY.

TCK

Test Clock (Input)

Test Clock provides the clocking function for the JTAG

boundary scan feature. TCK clocks state information

and data into the component on the rising edge of TCK

on TMS and TDI, respectively. Data is clocked out of the

component on the falling edge of TCK on TDO.

TDI

Test Data Input (Input)

TDI is the serial input that shifts JTAG instructions and

data into the tested component. TDI is sampled on the

rising edge of TCK during the SHIFT-IR and the SHIFT-

DR TAP (Test Access Port) controller states. During all

other TAP controller states, TDI is ignored. TDI uses an

internal weak pull-up.

TDO

Test Data Output (Output)

TDO is the serial output that shifts JTAG instructions

and data out of the component. TDO is driven on the

falling edge of TCK during the SHIFT-IR and SHIFT-DR

TAP controller states. Otherwise, TDO is three-stated.

TMS

Test Mode Select (Input)

TMS is decoded by the JTAG TAP to select the opera-

tion of the test logic. TMS is sampled on the rising edge

of TCK. To guarantee deterministic behavior of the TAP

controller, the TMS pin has an internal pull-up resistor.

Upgrade Present (Input)

The processor samples the Upgrade Present (UP) pin

in the clock before the falling edge of RESET. If it is Low,

the processor three-states its outputs immediately. UP

must remain asserted to keep the processor inactive.

The pin uses an internal pull-up resistor.

VOLDET (New, 168-Pin PGA Package only)

Voltage Detect (Output)

VOLDET provides an external signal to allow the system

to determine the CPU input power level (3 V or 5 V). For

the Am486DE2, the pin ties internally to VSS.

WB/WT (New)

Write-Back/Write-Through (Input)

WB/WT is sampled Low at RESET, and all cache-line

fills are write-through. WB/WT has an internal weak pull-

down. This pin should be tied Low for the Am486DE2

microprocessor.

W/R

Write/Read (Output)

A High output indicates a write cycle. A Low output in-

dicates a read cycle.

Note: The Am486DE2 microprocessor does not use the

CC5 pin used by some 3-V, clock-tripled, 486-based

processors. The corresponding pin on the Am486DE2

microprocessor is an Internal No Connect (INC).

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