AM486DE2 datasheet(35/52 Pages) AMD

35 / 52 page

Am486DE2 Microprocessor

tion vectors. The interrupt vector table for SMM has the

same format as for Real mode. Until the interrupt vector

table is correctly initialized, the SMI handler must not

generate an exception (or software interrupt). Even

though hardware interrupts are disabled, exceptions

and software interrupts can still occur. Only a correctly

written SMI handler can prevent internal exceptions.

When new exception vectors are initialized, internal ex-

ceptions can be serviced. The restrictions follow:

s Due to the Real mode style of base address

formation, an interrupt or exception cannot transfer

control to a segment with a base address of more

than 20 bits.

s An interrupt or exception cannot transfer control to a

segment offset of more than 16 bits.

s If exceptions or interrupts are allowed to occur, only

the Low order 16 bits of the return address are

pushed onto the stack. If the offset of the interrupted

procedure is greater than 64 Kbytes, it is not possible

for the interrupt/exception handler to return control

to that procedure. (One workaround is to perform

software adjustment of the return address on the

stack.)

s The SMBASE Relocation feature affects the way the

CPU returns from an interrupt or exception during an

SMI handler.

Note: The execution of an IRET instruction enables

Non-Maskable Interrupt (NMI) processing.

HALT during SMM

HALT should not be executed during SMM, unless in-

terrupts have been enabled. Interrupts are disabled on

entry to SMM. INTR and NMI are the only events that take

the CPU out of HALT within SMM.

Relocating SMRAM to an Address above 1 Mbyte

Within SMM (or Real mode), the segment base registers

can be updated only by changing the segment register.

The segment registers contain only 16 bits, which allows

only 20 bits to be used for a segment base address (the

segment register is shifted left 4 bits to determine the

segment base address). If SMRAM is relocated to an

address above 1 Mbyte, the segment registers can no

longer be initialized to point to SMRAM.

These areas can still be accessed by using address

override prefixes to generate an offset to the correct

address. For example, if the SMBASE has been relo-

cated immediately below 16M, the DS and ES registers

are still initialized to 0000 0000h. Data in SMRAM can still

be accessed by using 32-bit displacement registers:

move esi,OOFFxxxxh;64K segment immediately

below 16M

move ax,ds:[esi]

AM486DE2 датащи(PDF) 35 Page - Advanced Micro Devices

AM486DE2 датащи(HTML) 35 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

датащи скачать

ссылки URL