USB3300 datasheet(34/55 Pages) SMSC

34 / 55 page

Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface

Datasheet

Revision 1.08 (11-07-07)

SMSC USB3300

DATASHEET

In Figure 6.7, "ULPI Receive" the PHY asserts DIR to take control of the data bus from the Link. The

assertion of DIR and NXT in the same cycle contains additional information that Rxactive has been

asserted. When NXT is de-asserted and DIR is asserted, the RXD CMD data is transferred to the Link.

After the last byte of the USB receive packet is transferred to the PHY, the linestate will return to idle.

The ULPI full speed receiver operates according to the UTMI/ULPI specification. In the full speed case,

the NXT signal will assert only when the Data bus has a valid received data byte. When NXT is low

with DIR high, the RXD CMD is driven on the data bus.

In full speed, the USB3300 will not issue a Rxactive de-assertion in the RXD CMD until the DP/DM

linestate transition to idle. This prevents the Link from violating the two full speed bit times minimum

turn around time.

6.1.8.1

Disconnect Detection

A High Speed host must detect a disconnect by sampling the transmitter outputs during the long EOP

transmitted during a SOF packet. The USB3300 only looks for a high speed disconnect during the long

EOP where the period is long enough for the disconnect reflection to return to the host PHY. When a

high speed disconnect occurs the USB3300 will return a RXD CMD and set the host disconnect bit in

the ULPI interrupt status register (address 13h).

When in FS or LS modes, the Link is expected to handle all disconnect detection.

6.1.9

Low Power Mode

Low Power Mode is a power down state to save current when the USB session is suspended. The

Link controls when the PHY is placed into or out of Low Power Mode. In Low Power Mode all of the

circuits are powered down except the interface pins, full speed receiver, VBUS comparators, and ID

comparator.

6.1.9.1

Entering Low Power/Suspend Mode

To enter Low Power Mode, the Link will write a 0 or clear the SuspendM bit in the Function Control

CLKOUT, drive the clock low. Once the clock is stopped, the PHY will enter a low power state to

conserve current.

Figure 6.7 ULPI Receive

DIR

CLK

DATA[7:0]

STP

NXT

Rxd

Cmd

Idle

Turn

around

PID

Rxd

Cmd

Turn

around

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