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USB3300 датащи(PDF) 19 Page - SMSC Corporation |
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USB3300 датащи(HTML) 19 Page - SMSC Corporation |
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19 / 55 page ![]() Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet SMSC USB3300 19 Revision 1.08 (11-07-07) DATASHEET Chapter 6 Architecture Overview The USB3300 architecture can be broken down into the following blocks shown in Figure 6.1, "Simplified USB3300 Architecture" below. 6.1 ULPI Digital The USB3300 uses the industry standard ULPI digital interface to facilitate communication between the PHY and Link (device controller). The ULPI interface is designed to reduce the number of pins required to connect a discrete USB PHY to an ASIC or digital controller. For example, a full UTMI+ Level 3 OTG interface requires 54 signals while a ULPI interface requires only 12 signals. The ULPI interface is documented completely in the “UTMI+ Low Pin Interface (ULPI) Specification” document (www.ulpi.org). The following sections highlight the key operating modes of the USB3300 digital interface. Figure 6.1 Simplified USB3300 Architecture ULPI Digital OTG Module DATA[7:0] Internal Regulator & POR Bias Gen. CLKOUT NXT DIR STP VDD3.3 XTAL & PLL VBUS ID VDD3.3 DP DM USB3300 RBIAS HS XCVR FS/LS XCVR Resistors |
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