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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TDP142 датащи(PDF) 8 Page - Texas Instruments |
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TDP142 датащи(HTML) 8 Page - Texas Instruments |
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8 / 36 page  8 TDP142 SLLSEZ1C – SEPTEMBER 2017 – REVISED MAY 2019 www.ti.com Product Folder Links: TDP142 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated 6.8 Timing Requirements MIN NOM MAX UNIT tDIFF_DLY Differential Propagation Delay See Figure 7 300 ps tR, tF Output Rise/Fall time (see Figure 9) 20%-80% of differential voltage measured 1 inch from the output pin 40 ps tRF_MM Output Rise/Fall time mismatch 20%-80% of differential voltage measured 1 inch from the output pin 2.6 ps 6.9 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DPEN and HPDIN tDPEN_DEBOUNCE DPEN and HPDIN debounce time when transitioning from H to L. 2 10 ms I2C (Refer to Figure 6) fSCL I2C clock frequency 1 MHz tBUF Bus free time between START and STOP conditions 0.5 µs tHDSTA Hold time after repeated START condition. After this period, the first clock pulse is generated 0.26 µs tLOW Low period of the I2C clock 0.5 µs tHIGH High period of the I2C clock 0.26 µs tSUSTA Setup time for a repeated START condition 0.26 µs tHDDAT Data hold time 0 μs tSUDAT Data setup time 50 ns tR Rise time of both SDA and SCL signals 120 ns tF Fall time of both SDA and SCL signals 20 × (V(I2C)/5.5 V) 120 ns tSUSTO Setup time for STOP condition 0.26 μs Cb Capacitive load for each bus line 150 pF |
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