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TDP142

SLLSEZ1C – SEPTEMBER 2017 – REVISED MAY 2019

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Pin Functions (continued)

PIN

I/O

DESCRIPTION

NAME

NO.

(2)

Not a fail-safe I/O. Actively driving pin high while VCC is removed results in leakage voltage on VCC pins.

I2C_EN

17

4 Level I

I2C Programming Mode or GPIO Programming Select. I2C is only disabled when this pin is ‘0".

0 = GPIO mode (I2C disabled).

R = TI Test Mode (I2C enabled at 3.3 V).

F = I2C enabled at 1.8 V.

1 = I2C enabled at 3.3 V.

INDP3p

18

Diff I

DP Differential positive input for DisplayPort Lane 3.

INDP3n

19

Diff I

DP Differential negative input for DisplayPort Lane 3.

TEST1/SCL

21

2 Level I

When I2C_EN=’0’, pull down with 10k or directly connect to ground. Otherwise this pin is I2C

clock. . When used for I2C clock pullup to I2C master's VCC I2C supply.

TEST2/SDA

22

2 Level I

When I2C_EN=’0’ , pull down with 10k or directly connect to ground. Otherwise this pin is I2C data.

When used for I2C data pullup to I2C master's VCC I2C supply.

DPEN/HPDIN

23

2 Level I

(Failsafe)

(PD)

DP Enable Pin. When I2C_EN = ‘0’, this pin will enable or disable DisplayPort functionality.

Otherwise, when I2C_EN is not "0", DisplayPort functionality is enabled and disabled through I2C

registers.

L = DisplayPort Disabled. (Pull-down with 10k resistor)

H = DisplayPort Enabled. (Pull-up with10k resistor)

When I2C_EN is not "0" this pin is an input for Hot Plug Detect (HPD) received from DisplayPort

sink. When this HPDIN is low for greater than 2 ms, all DisplayPort lanes are disabled.

AUXp

24

I/O, CMOS

This pin along with AUXN is used by the TDP142 for AUX snooping. See the Application and

Implementation section for more detail.

AUXn

25

I/O, CMOS

This pin along with AUXP is used by the TDP142 for AUX snooping. See the Application and

Implementation section for more detail.

RSVD6

26

I/O, CMOS

Reserved.(1)

RSVD7

27

I/O, CMOS

Reserved.(1)

SNOOPENZ/RSVD8

29(2)

I/O

(PD)

When I2C_EN ! = 0, this pin is reserved. When I2C_EN = 0 , this pin is SNOOPENZ (L = AUX

snoop enabled and H = AUX snoop disabled with all lanes active).

OUTDP3p

30

Diff O

DP Differential positive output for DisplayPort Lane 3.

OUTDP3n

31

Diff O

DP Differential negative output for DisplayPort Lane 3.

HPDIN/RSVD9

32(2)

I/O

(PD)

When I2C_EN ! = 0, this pin is reserved. When I2C_EN = 0, this pin is an input for Hot Plug Detect

received from DisplayPort sink. When HPDIN is low for greater than 2ms, all DisplayPort lanes are

disabled.

OUTDP2p

33

Diff O

DP Differential positive output for DisplayPort Lane 2.

OUTDP2n

34

Diff O

DP Differential negative output for DisplayPort Lane 2.

RSVD10

35

I

Reserved.(1)

OUTDP1n

36

Diff O

DP Differential negative output for DisplayPort Lane 1.

OUTDP1p

37

Diff O

DP Differential positive output for DisplayPort Lane 1.

RSVD11

38

I

Reserved.(1)

OUTDP0n

39

Diff O

DP Differential negative output for DisplayPort Lane 0.

OUTDP0p

40

Diff O

DP Differential positive output for DisplayPort Lane 0.

GND

Thermal Pad

G

Ground.