SM320VC33, SMJ320VC33

SGUS034F – FEBRUARY 2001 – REVISED JUNE 2015

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6.18 Switching Characteristics for EXTCLK, All Modes

over recommended operating conditions, all modes (see Figure 3 and Figure 4)

PARAMETER

MIN

TYP

MAX

UNIT

Vmid

Midlevel, used to measure duty cycle

0.5 × DVDD

V

x1 mode

2(1)

4.5

7(1)

td(EXTCLK-H)

Delay time, EXTCLK to H1 and H3

ns

x0.5 mode

2(1)

4.5

7(1)

tr(H)

Rise time, H1 and H3

3(1)

ns

tf(H)

Fall time, H1 and H3

3(1)

ns

td(HL-HH)

Delay time, from H1 low to H3 high or from H3 low to H1 high

–1.5(1)

2(1)

ns

x5 PLL mode

1 / (5 × ƒext)

tc(H)

Cycle time, H1 and H3

x1 mode

1 / ƒext

ns

x0.5 mode

2 / ƒext

(1)

Not production tested

6.19 Switching Characteristics for Memory Read/Write for STRB

over recommended operating conditions for memory read/write

(1) (see Figure 5 through Figure 7)

PARAMETER

MIN

MAX

UNIT

td(H1L-SL)

Delay time, H1 low to STRB low

–1(2)

3

ns

td(H1L-SH)

Delay time, H1 low to STRB high

–1(2)

3

td(H1H-RWL)W

Delay time, H1 high to R/W low (write)

–1(2)

3

td(H1L-A)

Delay time, H1 low to address valid

–1(2)

3

td(H1H-RWH)W

Delay time, H1 high to R/W high (write)

–1(2)

3

td(H1H-A)W

Delay time, H1 high to address valid on back-to-back write cycles (write)

–1(2)

3(2)

tv(H1L-D)W

Valid time, data after H1 low (write)

5

th(H1H-D)W

Hold time, data after H1 high (write)

0(2)

5

(1)

These timings assume a similar loading of 30 pF on all pins.

(2)

Not production tested

6.20 Switching Characteristics for XF0 and XF1 when Executing LDFI or LDII

over recommended operating conditions for XF0 and XF1 when executing LDFI or LDII (see Figure 8)

PARAMETER

MIN

MAX

UNIT

td(H3H-XF0L)

Delay time, H3 high to XF0 low

3

ns

6.21 Switching Characteristics for XF0 when Executing STFI or STII

over recommended operating conditions for XF0 when executing STFI or STII (see Figure 9)

PARAMETER

MIN

MAX

UNIT

td(H3H-XF0H)

Delay time, H3 high to XF0 high(1)

3

ns

(1)

XF0 is always set high at the beginning of the execute phase of the interlock-store instruction. When no pipeline conflicts occur, the

address of the store is also driven at the beginning of the execute phase of the interlock-store instruction. However, if a pipeline conflict

prevents the store from executing, the address of the store will not be driven until the store can execute.

6.22 Switching Characteristics for XF0 and XF1 when Executing SIGI

over recommended operating conditions for XF0 and XF1 when executing SIGI (see Figure 10)

PARAMETER

MIN

MAX

UNIT

td(H3H-XF0L)

Delay time, H3 high to XF0 low

3

ns

td(H3H-XF0H)

Delay time, H3 high to XF0 high

3

14

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