SM320VC33 datasheet(36/53 Pages) TI2

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SM/SMJ320VC33

RpU

RESET

XF0

MCBL/MP

DVDD

RESET

SM320VC33, SMJ320VC33

SGUS034F – FEBRUARY 2001 – REVISED JUNE 2015

www.ti.com

When MCBL/MP = 1, the reset and interrupt vectors are hard-coded within the internal ROM. Because this is a

read-only device, these vectors cannot be modified. To enable user-defined interrupt routines, the internal

vectors contain fixed values that point to an internal section of SRAM beginning at 0x809FC1. Code execution

begins at these locations, so it is important to place branch instructions (to the interrupt routine) at these

locations and not vectors.

The bootloader program requires a small stack space for calls and returns. Two SRAM locations at 0x809800

and 0x809801 are used for this stack. Do not boot load data into these locations because it will corrupt the

bootloader program runtime stack. After the boot-load operation is complete, a program can reclaim these

locations. The simplest solution is to begin a program stack or uninitialized data section at 0x809800.

For additional details on bootloader operation including the bootloader source code, see the TMS320C3x User’s

Guide (SPRU031).

A bit I/O line or external logic can be used to safely disable the MCBL mode after bootloading is complete.

However, to ensure proper operation, the CPU should not be currently executing code or using external data as

the change takes place. In the following example, the XF0 pin is tri-state on reset, which allows the pullup

resistor to place the DSP in MCBL mode. The following code, placed at the beginning of an application then

causes the XF0 pin to become an active-logic-low output, changing the DSP mode to MP. The cache-enable and

RPTS instructions are used because they cause the LDI instruction to be executed multiple times even though it

has been fetched only once (before the mode change). In other words, the RPTS instruction acts as a one-level-

deep program cache for externally executed code. If the application code is to be executed from internal RAM,

no special provisions are needed.

LDI

8000h,ST ; Enable the cache

RPTS

; RPTS will fetch the following opcode 1 time

LDI

2h, IOF

; Drive MCBL/MP=0 for several cycles allowing

; the pipeline to clear

Figure 31. Changing Bootload Select Pin

8.2.13 JTAG Emulation

Though the 320VC33 contains a JTAG debug port which allows multiple JTAG enabled chips to be daisy-

chained, boundary scan of the pins is not supported. If the pin scan path is selected, it will be routed through a

null register with a length of one. For additional information concerning the emulation interface, see JTAG/MPSD

Emulation Technical Reference (SPDU079).

8.2.14 Designing a Target System Emulator Connector (14-Pin Header)

JTAG target devices support emulation through a dedicated emulation port. This port is a superset of the test

access port standard and is accessed by the emulator. To communicate with the emulator, the target system

must have a 14-pin header (two rows of seven pins) with the connections that are shown in Figure 32. Table 7

describes the emulation signals.

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