ADC12L030CIWM datasheet(6/35 Pages) NSC

6 / 35 page

DC and Logic Electrical Characteristics

The following specifications apply for V

+ =V

A+=VD+ = +3.3 VDC,VREF+ = +2.500 VDC,VREF−=0VDC, 12-bit + sign conver-

sion mode, f

CK =fSK = 5 MHz, RS =25

Ω, source impedance for V

REF+ and VREF−

≤ 25Ω, fully-differential input with fixed

1.250V common-mode voltage, and 10(t

CK) acquisition time unless otherwise specified. Boldface limits apply for TA =TJ =

MIN to TMAX; all other limits TA =TJ = 25˚C. (Notes 7, 8, 9)

Symbol

Parameter

Conditions

Typical

(Note 10)

Limits

(Note 11)

Units

(Limits)

CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS

IN(1)

Logical “1” Input Voltage

+ = 3.6V

2.0

V (min)

IN(0)

Logical “0” Input Voltage

+ = 3.0V

0.8

V (max)

IN(1)

Logical “1” Input Current

IN = 3.3V

0.005

1.0

µA (max)

IN(0)

Logical “0” Input Current

IN = 0V

−0.005

−1.0

µA (min)

DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS

OUT(1)

Logical “1” Output Voltage

+ = 3.0V, I

OUT = −360 µA

2.4

V (min)

+ = 3.0V, I

OUT =−10µA

2.9

V (min)

OUT(0)

Logical “0” Output Voltage

+ = 3.0V, I

OUT = 1.6 mA

0.4

V (max)

OUT

TRI-STATE Output Current

OUT = 0V

−0.1

−3.0

µA (max)

OUT = 3.3V

0.1

3.0

µA (max)

Output Short Circuit Source Current

OUT =0V

6.5

mA (min)

−I

Output Short Circuit Sink Current

OUT =VD+16

8.0

mA (min)

POWER SUPPLY CHARACTERISTICS

D+

Digital Supply Current

Awake

1.1

1.5

mA (max)

CS = HIGH, Powered Down, CCLK on

600

µA

CS = HIGH, Powered Down, CCLK off

µA

A+

Positive Analog Supply Current

Awake

2.2

3.0

mA (max)

CS = HIGH, Powered Down, CCLK on

µA

CS = HIGH, Powered Down, CCLK off

0.1

µA

REF

Reference Input Current

Awake

µA

CS = HIGH, Powered Down

0.1

µA

AC Electrical Characteristics

The following specifications apply for V

+ =V

A+=VD+ = +3.3 VDC,VREF+ = +2.500 VDC,VREF−=0VDC, 12-bit + sign conver-

sion mode, t

r =tf = 3 ns, fCK =fSK = 5 MHz, RS =25

Ω, source impedance for V

REF+ and VREF−

≤ 25Ω, fully-differential input

with fixed 1.250V common-mode voltage, and 10(t

CK) acquisition time unless otherwise specified. Boldface limits apply for

A =TJ =TMIN to TMAX; all other limits TA =TJ = 25˚C. (Note 17)

Symbol

Parameter

Conditions

Typical

(Note 10)

Limits (Note 11)

Units (Limits)

Conversion Clock (CCLK) Frequency

MHz (max)

MHz (min)

Serial Data Clock SCLK Frequency

MHz (max)

Hz (min)

Conversion Clock Duty Cycle

% (min)

% (max)

Serial Data Clock Duty Cycle

% (min)

% (max)

Conversion Time

12-Bit + Sign or 12-Bit

44(t

CK)

44(t

CK)

(max)

8.8

µs (max)

8-Bit + Sign or 8-Bit

21(t

CK)

21(t

CK)

(max)

4.2

µs (max)

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