ADC12L030CIWM datasheet(29/35 Pages) NSC

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Application Information (Continued)

The reference voltage inputs are not fully differential. The

ADC12L030/2/4/8 will not generate correct conversions or

comparisons if V

REF

+ is taken below V

REF

−. Correct conver-

sions result when V

REF

+ and V

REF

− differ by 1V and remain,

at all times, between ground and V

+. The V

REF common

mode range, (V

REF

+ +V

REF

−)/2, is restricted to (0.1 x V

+)to

(0.6 x V

+). Therefore, with V

+ = 3.3V the center of the

reference ladder should not go below 0.33V or above 1.98V.

Figure 15 is a graphic representation of the voltage restric-

tions on V

REF

+ and V

REF

−.

4.0 ANALOG INPUT VOLTAGE RANGE

The ADC12L030/2/4/8’s fully differential ADC generate a

two’s complement output that is found by using the equa-

tions shown below:

for (12-bit) resolution the Output Code =

for (8-bit) resolution the Output Code =

Round off to the nearest integer value between −4096 to

4095 for 12-bit resolution and between −256 to 255 for 8-bit

resolution if the result of the above equation is not a whole

number.

Examples are shown in the table below:

REF

−

Digital Output

Code

+2.5V

+1V

+1.5V

0,1111,1111,1111

+2.500V

+2V

0,1100,1100,1101

+2.500V

+2.499V +2.500V

1,1111,1111,1111

+2.500V

+2.500V 1,0000,0000,0000

5.0 INPUT CURRENT

At the start of the acquisition window (t

A) a charging current

flows into or out of the analog input pins (A/DIN1 and

A/DIN2) depending on the input voltage polarity. The analog

input pins are CH0–CH7 and COM when A/DIN1 is tied to

MUXOUT1 and A/DIN2 is tied to MUXOUT2. The peak value

of this input current will depend on the actual input voltage

applied, the source impedance and the internal multiplexer

switch on resistance. With MUXOUT1 tied to A/DIN1 and

MUXOUT2 tied to A/DIN2 the internal multiplexer switch on

resistance is typically 1.6 k

Ω. The A/DIN1 and A/DIN2 mux

on resistance is typically 750

Ω.

6.0 INPUT SOURCE RESISTANCE

For low impedance voltage sources (<600

Ω), the input

charging current will decay, before the end of the S/H’s

acquisition time of 2 µs (10 CCLK periods with f

C = 5 MHz),

to a value that will not introduce any conversion errors. For

high source impedances, the S/H’s acquisition time can be

increased to 18 or 34 CCLK periods. For less ADC resolution

and/or slower CCLK frequencies the S/H’s acquisition time

may be decreased to 6 CCLK periods. To determine the

number of clock periods (N

c) required for the acquisition time

with a specific source impedance for the various resolutions

the following equations can be used:

12 Bit + Sign

C =[RS + 2.3] x fC x 0.824

8 Bit + Sign

C =[RS + 2.3] x fC x 0.57

Where f

C is the conversion clock (CCLK) frequency in MHz

and R

S is the external source resistance in k

Ω. Asanex-

ample, operating with a resolution of 12 Bits+sign,a5MHz

clock frequency and maximum acquisition time of 34 conver-

sion clock periods the ADC’s analog inputs can handle a

source impedance as high as 6 k

Ω. The acquisition time may

also be extended to compensate for the settling or response

time of external circuitry connected between the MUXOUT

and A/DIN pins.

An acquisition is started by a falling edge of SCLK and ends

with a rising edge of CCLK (see Timing Diagrams). If SCLK

and CCLK are asynchronous one extra CCLK clock period

may be inserted into the programmed acquisition time for

synchronization. Therefore, with asynchronous SCLK and

CCLK, the acquisition time will change from conversion to

conversion.

7.0 INPUT BYPASS CAPACITANCE

External capacitors (0.01 µF–0.1 µF) can be connected

between the analog input pins, CH0–CH7, and analog

ground to filter any noise caused by inductive pickup asso-

ciated with long input leads. These capacitors will not de-

grade the conversion accuracy.

01183043

FIGURE 15. V

REF Operating Range

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