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LM27213

www.ti.com

SNVS377A – FEBRUARY 2006 – REVISED MARCH 2013

Figure 22. RMS Input Ripple Current as a Percentage of DC Output Current

So for a design that must operate at a steady state load current of 12A, with 1.4V out and 8V in, the RMS input

ripple current would be about 37% of 12A or 4.4A RMS. A sufficient number of capacitors must be connected in

parallel to handle this current. For capacitors rated at 1.5A each, a minimum of 3 would be required. If it’s

desired to add enough bulk capacitance to control the input’s low frequency ripple voltage, the characteristic

impedance of the input power source must be well understood.

Bypassing Considerations

The LM27213 should have its supply pin (24) well bypassed. Generally a 1µF capacitor connected between the

Vdd pin and the SGND pin (23), should be adequate. It’s a good idea to add a resistor of about 10

Ω in series

with the input source to provide some decoupling from noise on the 5V rail. The LM27213’s own gate drive pulse

currents can corrupt the 5V rail enough to cause problems without this filter. There also needs to be a 1µF or

larger ceramic capacitor connected between the driver supply pin PVDD (48) and PGND (45). The bypass

capacitors should be located very close to the pins to provide a low inductance path. This is particularly important

for the PVDD bypass. This capacitor must supply all of the low-side gate drive pulse currents as well as the

charging current for the high-side bootstrap capacitor. It’s also a good idea to install a 0.1µF capacitor between

the VREF pin (11) and SGND. In addition, there should be small filter capacitors connected between the ILIM

and ILIMREF pins and the CMP and CMPREF pins. Typically, a 1200pF capacitor will prove adequate for this

purpose.

Current Sense Resistor

The maximum value allowed for the current sense resistor is a value equal to the desired load line slope.

Increasing beyond this value will make the load line excessively steep with no way to reduce the slope. Lower

values are permissible and values as low as 1m

Ω have been used successfully. The regulator will have a

tendency to exhibit excessive amounts of pulse jitter if the sense resistor is too small since the current sense

signal is reduced as well. One way to mitigate this problem is to add a little filtering to the load line setting

resistor R2 in Figure 21. A typical time constant to shoot for is approximately 500ns. So for R2 = 100

Ω,

something around a 4700pF capacitor should prove helpful. If this capacitor is made too large the result will be

large overshoot and undershoot in the response to load transients. See the section below on load line setting for

more information about choosing these resistors.

Load Line Setting Resistors

Resistors R1, R2, and the current sense resistor (see Figure 20) are used to control the slope of the load line. In

the simplest configuration R1 = 0 ohms and R2 is omitted. In this case the load line is nominally equal to the

current sense resistor value. For relatively low current designs this configuration can work acceptably well. At

higher current levels the DC drop across the power planes may well contribute an excessive error since the

distribution path between the sense resistor and the load is effectively in series with the current sense resistor,

and therefore, will steepen the load line. For designs with relatively steep load lines (3 m

Ω) the power dissipation

is also excessive at high currents. The solution is to lower the sense resistor value and add the R1, R2 divider to

synthesize a steeper slope. The load line is calculated from:

LL = Rs x (1+R1/R2)

(16)

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