VA

AGND

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I/O

ADC12DL040

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SNAS250D – FEBRUARY 2005 – REVISED APRIL 2013

DC and Logic Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.0V, VDR =

+2.5V, PD = 0V, VREF = +1.0V, fCLK = 40 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel

output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C

(1) (2) (3)

Typical

Limits

Units

Symbol

Parameter

Conditions

(4)

(4)

(Limits)

CLK, PD, OEA, OEB DIGITAL INPUT CHARACTERISTICS

VIN(1)

Logical “1” Input Voltage

VD = 3.6V

2.0

V (min)

VIN(0)

Logical “0” Input Voltage

VD = 3.0V

1.0

V (max)

IIN(1)

Logical “1” Input Current

VIN = 3.3V

10

µA

IIN(0)

Logical “0” Input Current

VIN = 0V

−10

µA

CIN

Digital Input Capacitance

5

pF

DA0–DA11, DB0-DB11 DIGITAL OUTPUT CHARACTERISTICS

VDR = 2.5V

2.3

V (min)

VOUT(1)

Logical “1” Output Voltage

IOUT = −0.5 mA

VDR = 3V

2.7

V (min)

VOUT(0)

Logical “0” Output Voltage

IOUT = 1.6 mA, VDR = 3V

0.4

V (max)

VOUT = 2.5V or 3.3V

100

nA

IOZ

TRI-STATE® Output Current

VOUT = 0V

−100

nA

+ISC

Output Short Circuit Source Current

VOUT = 0V

−20

mA

−ISC

Output Short Circuit Sink Current

VOUT = VDR

20

mA

COUT

Digital Output Capacitance

5

pF

POWER SUPPLY CHARACTERISTICS

PD Pin = DGND, VREF = VA

58

72

mA (max)

IA

Analog Supply Current

PD Pin = VD

12

mA

PD Pin = DGND

12

14

mA (max)

ID

Digital Supply Current

PD Pin = VD , fCLK = 0

0

mA

PD Pin = DGND, CL = 5 pF

(5)

12

mA

IDR

Digital Output Supply Current

PD Pin = VD, fCLK = 0

0

mA

PD Pin = DGND, CL = 5 pF

(6)

210

258

mW (max)

Total Power Consumption

PD Pin = VD

36

mW

Rejection of Full-Scale Error with

PSRR1

Power Supply Rejection Ratio

54

dB

VA = 2.7V vs. 3.6V

(1)

The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided

current is limited per Note 4 under Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes above

VA or below GND by more than 100 mV. As an example, if VA is +3.3V, the full-scale input voltage must be ≤+3.4V to ensure accurate

conversions.

(2)

To specify accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3)

With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV.

(4)

Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing

Quality Level).

(5)

IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins,

the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C11 x

f11) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at

which that pin is toggling.

(6)

Excludes IDR. See Note 5.

Copyright © 2005–2013, Texas Instruments Incorporated

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