ADC12DL040CIVSSLASHNOPB datasheet(4/38 Pages) TI2

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AGND

VFloat

AGND

ADC12DL040

SNAS250D – FEBRUARY 2005 – REVISED APRIL 2013

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Pin Descriptions and Equivalent Circuits

Pin No.

Symbol

Equivalent Circuit

Description

ANALOG I/O

VINA+

Differential analog input pins. With a 1.0V reference voltage the

VINB+

differential full-scale input signal level is 2.0 VP-P with each input pin

voltage centered on a common mode voltage, VCM. The negative

input pins may be connected to VCM for single-ended operation, but

a differential input signal is required for best performance.

VINA−

VINB−

This pin is the reference select pin and the external reference input.

If (VA - 0.3V) < VREF < VA, the internal 1.0V reference is selected.

If AGND < VREF < (AGND + 0.3V), the internal 0.5V reference is

VREF

selected.

If a voltage in the range of 0.8V to 1.2V is applied to this pin, that

voltage is used as the reference. VREF should be bypassed to AGND

with a 0.1 µF capacitor when an external reference is used.

This is a four-state pin.

DF/DCS = VA, output data format is offset binary with duty cycle

stabilization applied to the input clock

DF/DCS = AGND, output data format is 2's complement, with duty

DF/DCS

cycle stabilization applied to the input clock.

DF/DCS = VRMA or VRMB , output data is 2's complement without

duty cycle stabilization applied to the input clock

DF/DCS = "float", output data is offset binary without duty cycle

stabilization applied to the input clock.

VRPA

VRPB

VRMA

VRMB

These pins are high impedance reference bypass pins. All these pins

should each be bypassed to ground with a 0.1 µF capacitor. A 10 µF

capacitor should be placed between the VRPA and VRNA pins and

between the VRPB and VRNB pins.

VRMA and VRMB may be loaded to 1mA for use as a temperature

VRNA

stable 1.5V reference. The remaining pins should not be loaded.

VRNB

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