ADC12DL040CIVSSLASHNOPB datasheet(5/38 Pages) TI2

5 / 38 page

VDR

DR GND

AGND

DGND

AGND

DGND

AGND

ADC12DL040

www.ti.com

SNAS250D – FEBRUARY 2005 – REVISED APRIL 2013

Pin No.

Symbol

Equivalent Circuit

Description

DIGITAL I/O

Digital clock input. The range of frequencies for this input is as

CLK

specified in the electrical tables with ensured performance at 40

MHz. The input is sampled on the rising edge.

OEA and OEB are the output enable pins that, when low, holds their

respective data output pins in the active state. When either of these

pins is high, the corresponding outputs are in a high impedance

state.

OEA

OEB

PD is the Power Down input pin. When high, this input puts the

converter into the power down mode. When this pin is low, the

converter is in the active mode.

When low, "A" and "B" data is present on it's respective data output

lines (Parallel Mode).

When high, both "A" and "B" channel data is present on the

"DA0:DA11" digital outputs (Multiplex Mode). The DB0/ABb pin is

used to synchronize the data.

MULTIPLEX

24–29

Digital data output pins that make up the 12-bit conversion results of

DA0–DA11

34–39

their respective converters. DA0 and DB0 are the LSBs, while DA11

and DB11 are the MSBs of the output word. Output levels are

43–47

DB1–DB11

TTL/CMOS compatible. Optimum loading is < 10pF.

52–57

When MULTIPLEX is low, this is DB0.

When MULTIPLEX is high this is the ABb signal, which is used to

DB0/ABb

synchronize the multiplexed data. ABb changes synchronously with

the Multiplexed "A" and "B" channels. ABb is "high" when "A"

channel data is valid and is "low" when "B" channel data is valid.

ANALOG POWER

Positive analog supply pins. These pins should be connected to a

9, 18, 19, 62,

quiet +3.0V source and bypassed to AGND with 0.1 µF capacitors

located within 1 cm of these power pins, and with a 10 µF capacitor.

3, 8, 10, 17,

AGND

The ground return for the analog supply.

20, 61, 64

DIGITAL POWER

Positive digital supply pin. This pin should be connected to the same

quiet +3.0V source as is VA and be bypassed to DGND with a 0.1 µF

33, 48

capacitor located within 1 cm of the power pin and with a 10 µF

capacitor.

32, 49

DGND

The ground return for the digital supply.

Positive driver supply pin for the ADC12DL040's output drivers. This

pin should be connected to a voltage source of +2.4V to VD and be

bypassed to DR GND with a 0.1 µF capacitor. If the supply for this

30, 51

VDR

pin is different from the supply used for VA and VD, it should also be

bypassed with a 10 µF capacitor. VDR should never exceed the

voltage on VD. All 0.1 µF bypass capacitors should be located within

1 cm of the supply pin.

The ground return for the digital supply for the ADC12DL040's output

drivers. These pins should be connected to the system digital

23, 31, 40,

DR GND

ground, but not be connected in close proximity to the

50, 58

ADC12DL040's DGND or AGND pins. See LAYOUT AND

GROUNDING for more details.

Submit Documentation Feedback

Product Folder Links: ADC12DL040

ADC12DL040CIVS/NOPB датащи(PDF) 5 Page - Texas Instruments

ADC12DL040CIVS/NOPB датащи(HTML) 5 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

датащи скачать

ссылки URL