VIH

VIL

SCL

P

S

VIH

VIL

SDA

tBUF

tHD;STA

tLOW

tR

tHD;DAT

tHIGH

tF

tSU;DAT

tSU;STA

tSU;STO

P

S

tVD;DAT

6

TMP116, TMP116N

SBOS740A – MAY 2017 – REVISED MAY 2019

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Product Folder Links: TMP116

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Copyright © 2017–2019, Texas Instruments Incorporated

Electrical Characteristics (continued)

minimum and maximum specifications are over –55°C to +125°C and V+ = 1.9 V to 5.5 V (unless otherwise noted); typical

specifications are at TA = 25°C and V+ = 3.3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

EEPROM

Programming time

7

ms

Number of writes

1,000

50,000

Times

Data retention time

10

100

Years

(1)

tVD;DATA = time for data signal from SCL low to SDA output (high to low, depending on which is worse).

6.6 Two-Wire Interface Timing

minimum and maximum specifications are over –55°C to 125°C and V+ = 1.9 V to 5.5 V (unless otherwise noted); typical

specifications are at TA = 25°C and V+ = 3.3 V; values are based on statistical analysis of samples tested during initial

release

MIN

MAX

UNIT

fSCL

SCL operating frequency

1

400

kHz

tBUF

Bus free time between STOP and START conditions

1300

ns

tHD;STA

Hold time after repeated START condition.

After this period, the first clock is generated.

600

ns

tSU;STA

Repeated START condition setup time

600

ns

tSU;STO

STOP condition setup time

600

ns

tHD;DAT

Data hold time

0

ns

tVD;DAT

Data valid time(1)

0.9

µs

tSU;DAT

Data setup time

100

ns

tLOW

SCL clock low period

1300

ns

tHIGH

SCL clock high period

600

ns

tF – SDA

Data fall time

20 × (V+ / 5.5)

300

ns

tF, tR – SCL

Clock fall and rise time

300

ns

tR

Rise time for SCL

≤ 100 kHz

1000

ns

Serial bus timeout (SDA bus released if there is no clock)

20

40

ms

Figure 1. Two-Wire Timing Diagram